AD9952/PCB Analog Devices Inc, AD9952/PCB Datasheet - Page 21

• Manufacturer Part Number: AD9952/PCB
• Description: BOARD EVAL FOR AD9952
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r
• Type: DDS (Direct Digital Synthesis)r

Specifications of AD9952/PCB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD9952

(MSB)
After the completion of Phase 2, the AD9952 serial port
controller expects the next eight SCLK rising edges to be a new
instruction byte, followed by an appropriate number of data
bytes. See the Example Operation section of this document for
details.
All data written into the serial port is clocked into the I/O
buffer on the rising edge of SCLK. All data read back from the
serial port is clocked out on the falling edge of SCLK. Note that
the readback operation reads data from registers, not the I/O
buffers. If new data has been written to an I/O buffer, but an
I/O update has not occurred, the old data stored in the register
is read back (see Step 2: Transfer of I/O Buffers to Registers).
Also, the serial I/O port speed of 25 Mbps refers solely to the
speed of SCLK during a write operation. As the AD9952 does
not generate data, the readback operation is considered a debug
feature and is not supported beyond 1 Mbps.
Instruction Byte Details
The instruction byte contains the following information.
D7
R/ W
R/ W
write data transfer occurs after the instruction byte write. Logic
High indicates a read operation; a Logic 0 indicates a write
operation.
X, X—Bit 6 and Bit 5, respectively, of the instruction byte are
don’t care.
A5, A4, A3, A2, A1—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0,
respectively, of the instruction byte determine which register is
accessed during the data transfer portion of the communication
cycle.
Step 2: Transfer of I/O Buffers to Registers
When the desired setup data is written via the serial port to the I/O
buffers, the registers must be updated by issuing an I/O update
signal on the I/O UPDATE pin. The I/O update signal consists of a
logic high pulse (DVDD_I/O) on the I/O UPDATE pin.
—Bit 7 of the instruction byte determines whether a read or
D6
X
D5
X
D4
A5
D3
A4
D2
A3
D1
A2
D0
A1
(LSB)
Rev. B | Page 21 of 28
As shown in Figure 24, the I/O update pulse is sampled
synchronously by the AD9952 on the rising edge of
SYNC_CLK. Therefore, the I/O update pulse needs to be set up
to the rising edge of the SYNC_CLK signal.
To transfer data without having to monitor the SYNC_CLK
signal and without having to guarantee setup time, an alternate
method is to provide an I/O update pulse for more than one
SYNC_CLK period (more than four SYSCLK periods)
asynchronously. If this is done, the I/O update pulse overlaps
with at least one SYNC_CLK rising edge. However, there is no
guarantee of which SYNC_CLK rising edge transfers the I/O
buffer data to the registers. This method introduces an
ambiguity of one SYNC_CLK cycle (four SYSCLK cycles) in the
calculation of the propagation delay and should be avoided if
propagation delay of data transfers is an important
consideration. This method is shown in Figure 25.
It should be noted that the exact transfer of data from the I/O
buffers to the registers actually occurs one SYNC_CLK cycle
after the I/O update signal is detected by the AD9952, as shown
in Figure 26.
I/O UPDATE
SYNC_CLK
Figure 24. Setup Time for I/O Update Pulse for Synchronous Data Transfer
I/O UPDATE
SYNC_CLK
I/O UPDATE HIGH PULSE GREATER THAN 1 SYNC_CLK PERIOD
Figure 25. I/O Update Pulse in Asynchronous Data Transfer
TSU
SYNC_CLK SETUP TIME =
I/O UPDATE TO
DVDD I/O =
DVDD I/O =
3.3V
4ns
1.8V
6ns
AD9952