C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet - Page 160

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C8051F410-TB

Manufacturer Part Number
C8051F410-TB
Description
BOARD PROTOTYPING W/C8051F410
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F410-TB

Contents
Board
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F410
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F410/1/2/3
160
Bits7–0: P1MAT[7:0]: Port1 Match Value.
Bits7–0: P1MASK[7:0]: Port1 Mask Value.
R/W
R/W
Bit7
Bit7
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
These bits select which Port pins will be compared to the value stored in P1MAT.
0: Corresponding P1.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT.
R/W
R/W
Bit6
Bit6
SFR Definition 18.15. P1MASK: Port1 Mask
SFR Definition 18.14. P1MAT: Port1 Match
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.1
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
R/W
R/W
Bit0
Bit0
0xCF
0xBF
00000000
Reset Value
Reset Value
11111111

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