C8051F005-TB Silicon Laboratories Inc, C8051F005-TB Datasheet - Page 78

• Manufacturer Part Number: C8051F005-TB
• Description: BOARD PROTOTYPING W/C8051F005
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005-TB

• Contents: Board
• Data Bus Width: 8 bit
• Silicon Manufacturer: Silicon Laboratories
• Core Architecture: 8051
• Silicon Family Name: C8051F00x
• Kit Contents: Board
• Features: JTAG Connector, Debug Adapter Interface, Analog I/O Configuration
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F005
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority
interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority
level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher
priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
10.4.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock
cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is
pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending
interrupt.
serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction
followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle
to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4
clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
Reset
External Interrupt 0 (/INT0)
Timer 0 Overflow
External Interrupt 1 (/INT1)
Timer 1 Overflow
Serial Port (UART)
Timer 2 Overflow (or EXF2)
Serial Peripheral Interface
SMBus Interface
ADC0 Window Comparison
Programmable Counter Array 0
Comparator 0 Falling Edge
Comparator 0 Rising Edge
Comparator 1 Falling Edge
Comparator 1 Rising Edge
Timer 3 Overflow
ADC0 End of Conversion
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
Unused Interrupt Location
External Crystal OSC Ready
Interrupt Source
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being
Interrupt
Table 10.4. Interrupt Summary
0x00AB
0x00A3
0x000B
0x001B
0x002B
0x003B
0x004B
0x005B
0x006B
0x007B
0x008B
0x009B
0x0000
0x0003
0x0013
0x0023
0x0033
0x0043
0x0053
0x0063
0x0073
0x0083
0x0093
Vector
Priority
Order
Top
Rev. 1.7
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI (SCON.0)
TI (SCON.1)
TF2 (T2CON.7)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
ADWINT (ADC0CN.2)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3 (TMR3CN.7)
ADCINT (ADC0CN.5)
IE4 (PRT1IF.4)
IE5 (PRT1IF.5)
IE6 (PRT1IF.6)
IE7 (PRT1IF.7)
None
XTLVLD (OSCXCN.7)
SI (SMB0CN.3)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
Interrupt-Pending Flag
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Always enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
ESPI0 (EIE1.0)
ESMB0 (EIE1.1)
EWADC0 (EIE1.2)
EPCA0 (EIE1.3)
ECP0F (EIE1.4)
ECP0R (EIE1.5)
ECP1F (EIE1.6)
ECP1R (EIE1.7)
ET3 (EIE2.0)
EADC0 (EIE2.1)
EX4 (EIE2.2)
EX5 (EIE2.3)
EX6 (EIE2.4)
EX7 (EIE2.5)
Reserved (EIE2.6)
EXVLD (EIE2.7)
Enable
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