EVK1060A Atmel, EVK1060A Datasheet - Page 14

• Manufacturer Part Number: EVK1060A
• Description: KIT EVAL FOR AT42QT1060-MMU
• Manufacturer: Atmel
• Series: Quantum, QTouch™r

Specifications of EVK1060A

• Sensor Type: Touch, Capacitive
• Sensing Range: 1 Button/Key
• Interface: I²C
• Sensitivity: 2mm ~ 5mm Pad Widths
• Voltage - Supply: 3V
• Embedded: No
• Utilized Ic / Part: AT42QT1060
• Silicon Manufacturer: Atmel
• Silicon Core Number: AT42QT1060-MMU
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Capacitive Touch
• Silicon Family Name: QT1060
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. I
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.3.1
14
2
C-compatible Communications
I
I
Data Read/Write
2
2
AT42QT1060
C-compatible Protocol
C-compatible Address
Protocol
Signals
Clock Stretching
Writing Data to the Device
The I
page
The I
A third line, CHG, is used to signal when the device has seen a change in the status byte:
The device has an internal monitor that resets its I
I
important that no other device on the bus clock stretches for 14 ms, otherwise the monitor will
reset the I
If the device is configured to run in stand-alone mode, the monitor will be turned off.
There is one preset I
The sequence of events required to write data to the device is shown next.
Table 5-1.
2
Key
S
SLA+W
A
C-compatible line is held low, without the other line changing, for more than about 14 ms. It is
• SDA - Serial Data
• SCL - Serial Clock
• CHG: Open-drain, active low when any capacitive key in the key mask has changed state or
any input line has changed state since the last I
status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status
bytes change back to their original state before the host has read the status bytes (for
example, a touch followed by a release), the CHG line will be held low. In this case, a read to
any memory location will clear the CHG line.
2
2
17) and supports multibyte reads and writes. The maximum clock rate is 100 kHz.
C-compatible interface requires two signals to operate:
C-compatible protocol is based around access to an address table (see
2
C-compatible hardware and transfers with the chip may be corrupted.
Description of Write Data Bits
S
2
C-compatible address of 0x12. This is not changeable.
SLA+W
A
Host to Device
MemAddress
Description
Start condition
Slave address plus write bit
Acknowledge bit
2
C-compatible read. After reading the two
A
2
C-compatible hardware if either
Data
Device to Host
A
P
9505E–AT42–02/09
Figure 6-1 on