AD8251-EVALZ Analog Devices Inc, AD8251-EVALZ Datasheet - Page 3

• Manufacturer Part Number: AD8251-EVALZ
• Description: BOARD EVALUATION FOR AD8251 PGA
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8251-EVALZ

• Channels Per Ic: 1 - Single
• Amplifier Type: Instrumentation
• Output Type: Single-Ended
• Slew Rate: 20 V/µs
• -3db Bandwidth: 10MHz
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 4.1mA
• Voltage - Supply, Single/dual (±): 5 V ~ 15 V
• Board Type: Fully Populated
• Utilized Ic / Part: AD8251
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -

Latched Gain Mode
Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using WR as a
latch, allowing other devices to share A0 and A1. Figure 3 shows
a schematic using this method, known as latched gain mode.
(On the AD8251-EVALZ, remove the W1, W2, and W3 jumpers,
and drive A0, A1, and WR with external logic to test this gain
setting mode.) The AD8251 is in this mode when WR is held at
logic high or logic low, typically 5 V and 0 V, respectively. The
voltages on A0 and A1 are read on the downward edge of the
WR signal as it transitions from logic high to logic low. This
latches in the logic levels on A0 and A1, resulting in a gain
change. See the truth table listing in Table 4 for more informa-
tion on these gain changes.
Table 4. Truth Table Logic Levels for Latched Gain Mode
WR
High to low
High to low
High to low
High to low
Low to low
Low to high
High to high
1
2
Jumper W1, Jumper W2, and Jumper W3 must be removed and external
logic must be used to test latched gain mode.
X = don’t care.
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
1
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
–IN
+IN
10μF
10μF
0.1µF
0.1µF
Figure 3. Latched Gain Mode, G = 8
+15V
–15V
A1
X
X
X
Low
Low
High
High
+
–
AD8251
2
2
2
1
DGND
WR
A1
A0
REF
A0
Low
High
Low
High
X
X
X
G = PREVIOUS
STATE
2
2
2
1
DGND
WR
A1
A0
Gain
Change to 1
Change to 2
Change to 4
Change to 8
No change
No change
No change
G = 8
+5V
0V
+5V
0V
+5V
0V
Rev. 0 | Page 3 of 4
On power-up, the AD8251 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8251 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 upon power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, t
WR latches in the gain. Similarly, they must be held for a
minimum hold time of t
ensure that the gain is latched in correctly. After t
may change logic levels but the gain does not change (until the
next downward edge of WR ). The minimum duration that WR
can be held high is t
duration that WR can be held low. Digital timing specifications
are listed in the Specification section of the
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in Figure 4.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
A0, A1
WR
Figure 4. Timing Diagram for Latched Gain Mode
t
WR
WR-HIGH
-HIGH
HD
t
SU
after the downward edge of WR to
, and t
SU
, before the downward edge of
WR
t
HD
t
-LOW
W R-LOW
AD8251-EVALZ
is the minimum
AD8251
HD
, A0 and A1
data sheet.