ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet
ISL6551EVAL1
Specifications of ISL6551EVAL1
Related parts for ISL6551EVAL1
ISL6551EVAL1 Summary of contents
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... Application Note This application note highlights design considerations for a 200W, 470kHz, telecom power supply using Intersil’s ISL6551 ZVS Full- Bridge Controller and ISL6550 Supervisor And Monitor. The zero-voltage switching technique of the ISL6551 is presented in detail. A step-by-step design procedure for a 48V-to-3.3V@60A with 88% efficiency converter based on these two chips, incorporating both ZVS full bridge and current doubler topologies, is described ...
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... The ISL6551 is a ZVS full bridge controller that Intersil has designed for medium to high power AC/DC and DC/DC applications with ultra high efficiency requirements. The ...
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CLOCK UP1 UP2 LOW1 LOW2 VP SYNC1 1 SYNC2 LOW1’ 2 LOW2’ SYNC2 3 SYNC1 T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING) T3-T4=LOWER LEFT-LEG RESONANT PERIOD In the above Figure, T0 through ...
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VS I LO1 I LO2 WORST CASE I Q1 WORST CASE I Q2 WORST CASE I MAG I P WORST CASE SYNC1 1 SYNC2 LOW1’ 2 LOW2’ SYNC2 3 SYNC1 T0-RESDLY T0-T1=LOWER RIGHT-LEG ...
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T0 -->T1, QA-to-QD Power Transfer (Active) Period [Figure ON QC= OFF + Vin ...
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Q1 and Q2 are turned on during the freewheeling time, which could reduce the conduction losses and the reflected output current in the primary. The amount of the load current split into Q1 and Q2 depends on ...
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T4 --> T5, QC-to-QB Power Transfer Period [Figure 10 ON OFF + ...
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... INV_LOW DRIVE ON INV_SYNC DRIVE FIGURE 13. LOWER RIGHT-LEG RESONANT PERIOD Intersil Supervisor and Monitor: ISL6550 The ISL6550 is a precision flexible, VID-code-controlled reference and voltage monitor for high-end microprocessor and memory power supplies. It monitors various input signals, and supervises the systems with its outputs. The ISL6550 saves board space, design time, and system cost ...
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VREF5 error and external resistor divider error as well as the internal buffer offset. In the reference design, the output voltage can be programmed from 2.64V to 3.63V with 31.918mV step and +/-3% statics error over ...
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Converter Design This section presents a step-by-step design procedure for a 48V-to-3.3V, 200W, 470kHz with 88% efficiency converter using both ISL6551 and ISL6550 for telecom applications (i.e V =36V-to-75V). The converter is designed with IN secondary-referenced, peak current-mode control, and ...
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Vsynfet = Io x Rdsonsyn/2 is the channel drop of the synchronous FETs at half of the load (assuming that the output load is split evenly into both synchronous FETs during the freewheeling period), Vomax is the maximum output ...
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ESR and capacitance. dI ∆V • ---- - = ESL ESL dt Vo f(Istep) ∆V ∆V ESL Istep FIGURE 16. TYPICAL TRANSIENT RESPONSE WAVEFORM Thus, ...
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Ib I ∆ Ia CASE – 0 ∆ 2 I • Irms4 ------- - – • WHERE Ic = ---------------- - ...
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... FET to zero volt before they are turned on. The turn-on losses of the lower FETs can be approximated with EQ. 45. The turn-off losses of primary switches can be minimized with a high speed driver such as Intersil HIP2100. (EQ. 41) Ppriswon (EQ. 42) When the lower FET is turned off, its corresponding upper ...
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EXPERIMENTAL RESULTS, prior to turn off the synchronous FET, help to achieve ZVT for the synchronous FETs at turn off. To achieve ZVT as discussed in previous lines, the synchronous FET drivers however should have ...
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Figure 17 shows the block diagram of the overall closed-loop system. PWM ISOLATION + - RAMP CURRENT TRANSFORMER ERROR AMPLIFIER - + FIGURE 17. BLOCK DIAGRAM OF CLOSED-LOOP SYSTEM This peak current mode controlled ...
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Special Notes for Configuring the ISL6551 The controller can be easily configured using Table 1 in the ISL6551 datasheet. In this section, several things that require the users’ attention are highlighted. For a detailed configuration, please refer to the device ...
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Heavy copper traces should be connected to the bias pins (VDD, VDDP1, VDDP2) and the ground pins (VSS and PGND) for heat spreading. • The copper ...
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START will not be latched. The latch can be reset by the PEN signal, which is controlled by the input voltage, the mechanical switch, and the thermal condition of the converter. If latching the converter off ...
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TABLE 2. DESIGN PARAMETER REQUIREMENTS (Continued) PARAMETER CONDITION MAIN TRANSFORMER Imag Lmag=60uH (Limited by Core), Vo=3.63V, Fsw Ipripeak Vin=75V, Vo=3.63V Iprms VIN=75V, Vo=3.63V Isrms Vin=75V, Vo=3.63V N Limited by Core Nmax Vin=36V, Vomax=3.63V, Vmisc=0.3V, Dmaxav=0.85 CURRENT TRANSFORMER Ncs PRIMARY SWITCHES ...
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Thoughts After Design Users can use these thoughts to make some possible improvements of the reference design. 1. The input capacitors (C13-C15) can be replaced with ceramic capacitors with smaller footprints such as TDK SMT1812 C4532X7R2A105M. 2. The output capacitors ...
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... Figure 21, helps eliminate the shoot-through currents through the primary switches during switching transitions. Figures 22 and 23 show the resonant delay and the dead time set at the ISL6551 prior to be processed through pulse transformers (T3 andT5) and bridge drivers (Intersil HIP2100). ...
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The dead time and the resonant delay, with 2V as the turn-on threshold of primary switches, of one converter is summarized in Table 3. The real delays at the primary switches are shorter than the “delays” set at the ISL6551 ...
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FIGURE 24. SYNCHRONOUS DRIVE SIGNAL. CHANNEL 1: LOWER DRIVE SIGNAL AT ISL6551; CHANNEL 2: SYNCHRONOUS DRIVE SIGNAL; CHANNEL 3: LOWER DRIVE SIGNAL AT THE LOWER FET Switching Waveforms WINDING VOLTAGE AND CURRENT Figures show the voltage ...
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FIGURE 27. TRANSFORMER WAVEFORMS =3.3V, AND I =0A (SYN ON). CHANNEL 4: OUT OUT PRIMARY CURRENT (I ); CHANNEL 3: PRIMARY P VOLTAGE (VP); CHANNEL 2: SECONDARY VOLTAGE (VS FIGURE 28. TRANSFORMER WAVEFORMS AT V ...
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FIGURE 31. RESONANT TRANSITION AT V AND I =37A. CHANNEL 2: V OUT LOWER FET; CHANNEL 3: LOWER GATE DRIVE SIGNAL FIGURE 32. RESONANT TRANSITION (LOST =3.3V, AND I =0A. CHANNEL 2: V OUT OUT VOLTAGE OF ...
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As shown in Figures 35 and 36, the synchronous FETs are zero-voltage switching at turn on, and have negligible switching losses at turn off during the light load. Nevertheless, the two bumps, as shown in Figure 35, are caused by ...
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ISL6550. For instance, when R40 or R42 is somehow shorted by debris or solder, the output voltage would be programmed (the reference of ISL6550) and the local over-voltage setpoint is also moved up relative to the output ...
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Iout (A) FIGURE 44. EFFICIENCY CURVES FOR V =3.64V @~400 LFM OUT ...
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Output Load (A) FIGURE 47. LOWER FET (Q17) CASE TEMPERATURE ...
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Input Voltage (V) FIGURE 53. UPPER FET (Q14) CASE TEMPERATURE Input Voltage (V) FIGURE 54. LOWER FET (Q17) CASE TEMPERATURE 95 90 ...
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Input Voltage (V) FIGURE 59. OUTPUT INDUCTOR (L2) CASE TEMPERATURE As shown in the figures above, the current transformer and the main transformer are the hottest components. Without any airflow, their case ...
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FIGURE 63. TURN ON MASTER (CHANNEL 3 AND CHANNEL 1) FIRST. SLAVE: CHANNEL 4 AND CHANNEL 2 Figures 62 and Figure 63 show the interaction between master and slave units in two different turn-on sequences. When ...
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FIGURE 67. TRANSIENT RESPONSE FOR 3.3V AT 45A-60A STEP, 1A/us OUT FIGURE 68. TRANSIENT RESPONSE FOR 3.63V AT 0A-15A STEP, 1A/us OUT FIGURE 69. TRANSIENT RESPONSE FOR 3.63V AT 45A-60A STEP, ...
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PHASE FIGURE 72. PLANT FREQUENCY RESPONSE FOR 3.3V@38A RESISTIVE LOAD. RED-48V, BLUE-75V, AND BLACK-36V 4 1 FIGURE 73. FREQUENCY RESPONSE OF 1) PLANT (Vo/Ve), 2) FEEDBACK COMPENSATION, 3) DIFFERENTIAL AMPLIFIER, AND 4) OPEN LOOP FOR V IN RESISTIVE LOAD. RED-GAIN ...
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FIGURE 76. OPEN LOOP RESPONSE FOR 2.64V@60A CONSTANT CURRENT LOAD. RED-48V, BLUE- 75V, AND BLACK-36V FIGURE 77. OPEN LOOP RESPONSE FOR 3.3V@60A CONSTANT CURRENT LOAD. RED-48V, BLUE- 75V, AND BLACK-36V FIGURE 78. OPEN LOOP RESPONSE FOR 3.64V@60A CONSTANT CURRENT LOAD. ...
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In addition to the above loop measurement, the following presents some modeling results using the simplified loop system including the high-frequency correlation term as discussed in the Control Loop Design section on page 16. The feedback compensation and the differential ...
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Fequency (Hz) FIGURE 87. LOOP RESPONSE FOR 38A “PURE” RESISTIVE LOAD The measured loop and plant responses for 48V input and 3.3V output ...
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FIGURE 90. OUTPUT VOLTAGE RIPPLE (CHANNEL =75V, V =3.63V, AND I IN OUT FIGURE 91. OUTPUT VOLTAGE RIPPLE (CHANNEL =75V, V =3.63V, AND I IN OUT FIGURE 92. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT ...
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Output Start Up The start up characteristic of the output voltage heavily depends on the load. For a “pure” resistive load or an electronic load with low slew rate (0.01A/us), the output voltage comes up smoothly, as shown in Figures ...
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FIGURE 100. OUTPUT VOLTAGE STARTUP EXPANSION (CHANNEL =48V =60A, 1A/US ELECTRONIC CONSTANT OUT CURRENT MODE. CHANNEL 2: ERROR VOLTAGE; CHANNEL 3: VCLAMP VOLTAGE; CHANNEL 4: CURRENT RAMP (ISENSE). 100US/DIV. Output Turned Off Characteristic When ...
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... It turns off the synchronous FETs during the start up at low load conditions. Once the FETs are turned TABLE 8. EQUIPMENT LIST EQUIPMENT DESCRIPTIONS ISl6551EVAL1 Rev. B, #1, #2, #3, & 6653A S/N: 3621A-03425 2. Lamda LQ521 S/N: J 3570 3. XANTREX 100-10 S/N: 72963 4 ...
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... The ZVS technique of the ISL6551 full-bridge controller is presented. The superior performance of the ISL6551, with its BJ17 companions Intersil’s HIP2100 half-bridge driver and ISL6550 Supervisor And Monitor, has been demonstrated in the reference design of a 200W, 470kHz telecom power supply incorporating both full-bridge and current doubler topologies ...
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TERM DEFINITIONS Cin Input Capacitance Co Output Capacitance Coss Output Capacitance of MOSFET Cp Primary Capacitance of Transformer D Ratio of On-Time Interval of Lower FET to One Clock Period (1/Fclock), Duty Cycle dI Ripple Current thru Each Output Inductor ...
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TERM DEFINITIONS (Continued) Po Output Power Psynfet Power Dissipation of Synchronous FET Psynfetfr Losses of Syn FET in Freewheeling Period Pupfet Power Dissipation of Upper FET Qg Gate Charge of MOSFET at V Rcs Current Sense Resistor Rdsonpri Rds(on) of ...
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... Inverting Driver OUT OUT SYNN_G 4 5 GND GND C10 C11 MIC4421BM 1u Title SARTN Telecom Power Supply Schematics, 3.3V@60A Size Document Number A ISL6551EVAL1 Date TP1 D Si4842DY VS Reverse D26 R28 Voltage at D26 and D27, at least 40V 0 C64 L2 C 5.6n, 50V R46 DNP 0.8uH SARTN ...
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... HO LI R30 0 4 R31 HS HI DNP0603 HIP2100IB Q20 TP25 C63 1 DNP0603 C23 Title Telecom Power Supply Schematics, 3.3V@60A Size Document Number A ISL6551EVAL1 Date C13-C15 can be replaced with smaller footprint ceramic caps. D C15 1u Q13 Q14 SUD40N10-25 VS+ TP12 TP13 1 T2 R22 UP2_G 1 TP14 ...
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... ISL6550CIR R42 R43 C29 26.7k 110k SAICRTN R45 10k R47 26.7k Title Telecom Power Supply Schematics, 3.3V@60A SAICRTN Size Document Number A ISL6551EVAL1 Date: Thursday, April 18, 2002 Differential Amp. Output VOPOUT TP26 D31 LED TP27 SAICRTN START ENABLE TP28 R69 100 ...
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... EAO SHARE 11 12 R70 ISL6551IR C45 5.1K TP32 100p C47 470p, NPO, 5% C48 22n, NPO, 5% R74 30.1k Title Telecom Power Supply Schematics, 3.3V@60A SAICRTN TP34 Size Document Number A ISL6551EVAL1 Date SA+12V U1A OUT R48 49.9k C31 LM393D R49 30 R51 20k U1B ...
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... D21 LM393D D22 R91 100k U2B 5 + C55 7 OUT C56 0.1u LM393D SBICRTN Title Telecom Power Supply Schematics, 3.3V@60A Size Document Number A ISL6551EVAL1 Date R83 SB+12V 0 SA+12V C ENABLE R89 100k M8 34.3V Q23 8 Anode NC 33. Cathode Base 6 NC Collector 5 NC ...
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... OUT C58 DNP 2 - SAICRTN LM393D 2 SAICRTN R99 1M C60 100p SAICRTN U3B OUT 6 - LM393D SAICRTN START D131 3 BAS40-06LT1 ENABLE Title Telecom Power Supply Schematics, 3.3V@60A Size Document Number A ISL6551EVAL1 Date R93 R133 2.67k 2.67k R104 SYNOFF C 0 C59 0. Thursday, April 18, 2002 Sheet ...
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... LittleFuse R451010 Digi-Key S1012-03-ND Various Jumpers for JP1 &JP2 Various Various DT Magnetics 015138 Rev B Micrel Semiconductor MIC4421BM Intersil HIP2100IB Intersil ISL6550CIR Intersil ICL6551IR Texas Instrument TL431AID Infineon IL217AT Burndy KPA8CTP Vishay Siliconix Si4842DY On Semiconductor MMJT9410 Vishay Siliconix SUD40N10-25 On Semiconductor 2N7002LT1 On Semiconductor ...
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Item Quantity Reference 61 8 R6,R7,R12,R13,R14,R25, R28,R30 62 4 R8,R48,R60,R67 R10 65 1 R11 66 2 R77,R17 67 4 R20,R27,R56,R57 68 1 R22 69 4 R23,R24,R26,R33 70 5 R29,R31,R52,R53,R54 71 7 R32,R51,R55,R72,R87,R88, R96 72 3 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...