MAX11617EVSYS+ Maxim Integrated Products, MAX11617EVSYS+ Datasheet - Page 16

• Manufacturer Part Number: MAX11617EVSYS+
• Description: EVALUATION SYSTEM FOR MAX11617
• Manufacturer: Maxim Integrated Products

Specifications of MAX11617EVSYS+

• Number Of Adc's: 1
• Number Of Bits: 8, 10, 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Inputs Per Adc: 12 Single Ended or 6 Differential
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MAX11617
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The converted results are read back in a first-in-first-out
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-
ed from a multichannel scan. This does not apply to the
MAX11614/MAX11615 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
first result. Note that only the current conversion results
is read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during
Low-Power, 4-/8-/12-Channel, I
12-Bit ADCs in Ultra-Small Packages
Figure 10. Internal Clock Mode Read Cycles
Figure 11. External Clock Mode Read Cycle
16
A. SINGLE CONVERSION WITH INTERNAL CLOCK
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
S
1
S
SLAVE ADDRESS
______________________________________________________________________________________
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
7
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
S
1
S
t
ACQ
7
t
ACQ1
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
1 1
R
7
7
1 1
R
A
A
CLOCK STRETCH
t
CONV
t
1 1
R
1 1
R
CONV1
A
A
CLOCK STRETCH
t
t
ACQ
ACQ1
RESULT 1 (4 MSBs)
RESULT (4 MSBs)
RESULT 4 MSBs
8
8
t
ACQ2
t
CONV2
8
1
A
1
A
A
t
CONV
t
CONV1
RESULT 2 (8 LSBs)
RESULT (8 LSBs)
CLOCK STRETCH
RESULT 8 LSBs
t
t
ACQN
8
CONVN
8
8
RESULT 1 ( 4MSBs)
1
A
1
A
1
A
t
ACQ2
P or Sr
P OR Sr
8
1
1
conversion. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
When configured for external clock mode (CLK = 1),
the MAX11612–MAX11617 use the SCL as the conver-
sion clock. In external clock mode, the MAX11612–
MAX11617 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
1
A
RESULT N (4 MSBs)
t
NUMBER OF BITS
ACQN
NUMBER OF BITS
RESULT 1 (8 LSBs) A
8
8
2
1
1
A
C,
t
CONVN
RESULT N (8 LSBs)
RESULT N (4MSBs)
8
8
1
A
RESULT N (8LSBs)
1
A
P OR Sr
8
1
1
A
NUMBER OF BITS
External Clock
P or Sr
1
NUMBER OF BITS