MAX11615EVSYS+ Maxim Integrated Products, MAX11615EVSYS+ Datasheet - Page 11

• Manufacturer Part Number: MAX11615EVSYS+
• Description: EVALUATION SYSTEM FOR MAX11615
• Manufacturer: Maxim Integrated Products

Specifications of MAX11615EVSYS+

• Number Of Adc's: 1
• Number Of Bits: 8, 10, 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Inputs Per Adc: 8 Single or 4 Differential
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MAX11615
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

swing from (GND - 0.3V) to (V
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above V
The SGL/DIF of the configuration byte configures the
MAX11612–MAX11617 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[3:0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[3:0] (Table 4).
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±V
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11612–MAX11617 al-
ways operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
The MAX11612–MAX11617 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11612–MAX11617 and the master
at rates up to 1.7MHz. The MAX11612–MAX11617 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit ). Series resistors (R
protect the input architecture of the MAX11612–
MAX11617 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11612–MAX11617.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
DD
.
Single-Ended/Differential Input
REF
______________________________________________________________________________________
REF
/2. The digital output code is bina-
. A negative differential analog
2-Wire Digital Interface
12-Bit ADCs in Ultra-Small Packages
DD
+ 0.3V) without caus-
Unipolar/Bipolar
S
Low-Power, 4-/8-/12-Channel, I
) are optional. They
Bit Transfer
REF
.
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high (Figure 5). A repeated START condi-
tion (Sr) can be used in place of a STOP condition to
leave the bus active and the interface mode
unchanged (see the HS Mode section).
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11612–MAX11617 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Figure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
SDA
SCL
SDA
SCL
S
S
1
START and STOP Conditions
2
Sr
NOT ACKNOWLEDGE
Acknowledge Bits
ACKNOWLEDGE
8
P
9
2
C,
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