MAX1202EVL11-DIP Maxim Integrated Products, MAX1202EVL11-DIP Datasheet - Page 14

• Manufacturer Part Number: MAX1202EVL11-DIP
• Description: EVALUATION KIT FOR MAX1202 DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1202EVL11-DIP

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Inputs Per Adc: 8 Single or 4 Differential
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 7.5mW @ 133kSPS
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1202, MAX1203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The conversion must complete in some minimum time or
droop on the sample-and-hold capacitors might degrade
conversion results. Use internal clock mode if the clock
period exceeds 10µs or if serial-clock interruptions could
cause the conversion interval to exceed 120µs.
In internal clock mode, the MAX1202/MAX1203 generate
their own conversion clock. This frees the µP from run-
ning the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
14
______________________________________________________________________________________
DOUT
SCLK
SSTRB
DIN
SCLK
CS
CS
t
CSH
t
DV
t
CSS
t
DS
t
DH
t
SDV
t
Internal Clock
CL
t
CH
PD0 CLOCKED IN
convenience, at any clock rate from zero to 2MHz.
SSTRB goes low at the start of the conversion, then goes
high when the conversion is complete. SSTRB is low for
a maximum of 10µs, during which time SCLK should
remain low for best noise performance. An internal regis-
ter stores data while the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the next
falling clock edge produces the MSB of the conversion
at DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CS does not need to be held low once a
t
SSTRB
t
DO
t
SSTRB
t
CSH
t
TR
t
STR