MAX152EVKIT-DIP Maxim Integrated Products, MAX152EVKIT-DIP Datasheet - Page 7

• Manufacturer Part Number: MAX152EVKIT-DIP
• Description: EVALUATION KIT FOR MAX152/153
• Manufacturer: Maxim Integrated Products

Specifications of MAX152EVKIT-DIP

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Inputs Per Adc: 1 Single Ended
• Input Range: ±VREF
• Power (typ) @ Conditions: 4.5mW @ 400kSPS
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX152, MAX153
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once the MAX152 is in power-down mode, lowest sup-
ply current is drawn with MODE low (RD mode) due to
an internal pull-down resistor at this pin. In addition, for
minimum current consumption, other digital inputs
should remain high in power-down. Refer to the
Reference section for information on reducing refer-
ence current during power-down.
The MAX152 has two basic interface modes set by the
status of the MODE input pin. When MODE is low, the
converter is in the RD mode; when MODE is high, the
converter is set up for the WR-RD mode.
In RD mode, conversion control and data access are
controlled by the RD input (Figure 3). The comparator
inputs track the analog input voltage for the duration of
t P . A conversion is initiated by driving RD low. With µPs
that can be forced into a wait state, hold RD low until
output data appears. The µP starts the conversion,
waits, and then reads data with a single read instruction.
WR/RDY is configured as a status output (RDY) in RD
mode, where it can drive the ready or wait input of a
µP. RDY is an open-collector output (with no internal
pull-up) that goes low after the falling edge of CS and
goes high at the end of the conversion. If not used, the
WR/RDY pin can be left unconnected. The INT output
goes low at the end of the conversion and returns high
on the rising edge of CS or RD.
Figure 3. RD Mode Timing (MODE = 0)
___________________Digital Interface
PWRDN
D0-D7
RDY
INT
CS
RD
t RDY
t UP
t CSS
_______________________________________________________________________________________
Read Mode (MODE = 0)
WITH EXTERNAL
t ACCO
t CRD
PULL-UP
+3V, 8-Bit ADC with 1µA Power-Down
t CSH
VALID DATA
t DH
t P
t INTH
Figures 4 and 5 show the operating sequence for the
write-read (WR-RD) mode. The comparator inputs
track the analog input voltage for the duration of t P .
The conversion is initiated by a falling edge of WR.
When WR returns high, the 4 MSBs' flash result is
latched into the output buffers and the 4 LSBs' conver-
sion begins. INT goes low, indicating conversion end,
and the lower 4 data bits are latched into the output
buffers. The data is then accessible after RD goes low
(see Timing Characteristics ).
Figure 4. WR-RD Mode Timing (t
Figure 5. WR-RD Mode Timing (t
Mode (MODE = 1)
PWRDN
D0-D7
PWRDN
WR
INT
CS
RD
WR
INT
CS
RD
t CSS
t CSS
t UP
t UP
Write-Read Mode (MODE = 1)
t WR
t WR
t CWR
t ACC1
t INTL
t RD
t CSH
RD
t CSH
RD
t RD
> t
< t
t READ1
INTL
INTL
t ACC2
VALID DATA
t RI
t P
) (MODE = 1)
), Fastest Operating
t DH
t P
t READ2
t INTH
VALID DATA
t DH
7