CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 13

• Manufacturer Part Number: CDB53L21
• Description: BOARD EVAL FOR CS53L21 ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB53L21

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Data Interface: Serial
• Inputs Per Adc: 3 Single Ended
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 22.45mW @ 48kSPS, 2.5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS53L21
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1550

DS700DB1
3. HARDWARE MODE CONTROL
The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W
Control” and “CS53L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software
Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or when exiting Software Mode,
by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable.
3.1
Notes:
12-15 Reserved
00 - Reserved
01 - I/O Header MCLK / I/O Header clocks/data route through
FPGA
10 - Oscillator MCLK / I/O Header clocks/data route through FPGA
11 - Reserved
Routing
Figure 6
Figure 7
Figure 8
Figure 9
Signal
10
11
0
1
2
3
4
5
6
7
8
9
FPGA H/W Control
The “FPGA H/W Control” switch S3 sets up the CDB in 4 pre-defined routing topologies in Hardware Mode.
The tables and figures below describe each switch setting. The At-A-Glance Controls table provides a quick
reference for all presets.
1. The S[1] setting affects FPGA signal routing only and is independent of the
S[3:0]
H/W Control” switch S5. These settings must be made manually by the user and have to be consistent.
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
0111
Oscillator MCLK
I/O MCLK
CS53L21 Clocks, I/O Data
CS53L21 Clocks, I/O Data
General Description
S[3:2]
I/O Clocks/Data
I/O Clocks/Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 1. MCLK and Clock/Data Routing Options
At-A-Glance Controls
1) I/O masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) I/O masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) Oscillator masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) Oscillator masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
0 - CS53L21 Slave Routing
1 - CS53L21 Master Routing
S[1] (See Note 1.)
Detailed Description
M/S setting of the “CS53L21
0 - No Loopback Routing
1 - Reserved
CDB53L21
S[0]
13