SI5319-EVB Silicon Laboratories Inc, SI5319-EVB Datasheet
SI5319-EVB
Specifications of SI5319-EVB
Related parts for SI5319-EVB
SI5319-EVB Summary of contents
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S 5315-EVB U I SER Description The Si5315 Evaluation Board User’s Guide provides for a complete and simple evaluation of the functions, features, and performance of the Si5315-EVB. The Si5315 Synchronous Ethernet/Telecom attenuating clock multiplier has a comprehensive feature set, ...
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Si5315-EVB 1. Introduction The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock ...
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Si53315-EVB Input and Output Clocks Refer to the schematics, diagrams, and tables while reading this section. 2.1. Input Clocks The Si5315 has two differential clock inputs that are AC terminated and AC coupled before being presented to the Si5315. ...
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Si5315-EVB 2.4. Pin Configuration J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the Si5315. Each pin can be strapped to be either ...
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Connectors and LEDs 3.1. LEDs LED Color D1 Yellow D2 Red D3 Red D4 Red D5 Green D6 Green 3.2. Connectors, Headers, and Jumpers Refer to Figure 2 to locate the items described in this section. C7, C12, C16, ...
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Si5315-EVB *Note: Unused header pin locations should be left open. Table 4. Status Indication Header, J13 6 Table 3. Configuration Header, J12 J12 Pin J12.1 Not used* J12.2 SFOUT0 J12.3 SFOUT1 J12.4 FRQTBL J12.5 FRQSEL0 J12.6 FRQSEL1 J12.7 FRQSEL2 J12.8 ...
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Schematics VDD3 32 VDD2 10 VDD1 5 Rate0 11 Rate1 Preliminary Rev. 0.2 Si5315-EVB GND5 37 GND4 19 ...
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Si5315-EVB PAD Preliminary Rev. 0 ...
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Bill of Materials Item Qty Reference 1 6 C1,C2,C3,C13,C15,C19 2 11 C4,C7,C9,C10,C11,C12,C14, C16,C17,C18,C20 3 3 C5,C22,C25 5 2 C21,C24 6 2 C23,C26 D2,D3, D5, J1,J2,J4,J5,J6,J7, J8,J9,J10,J11 13 1 J12 14 ...
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Si5315-EVB Item Qty Reference C6, R6,R10,R13 10 Table 5. Si5315-EVB Bill of Materials Part FAN1540B 40 MHz Not Populated 10NF Jmpr_2pin 100 0 ohm ...
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Layout Figure 5. Silkscreen Top Preliminary Rev. 0.2 Si5315-EVB 11 ...
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Si5315-EVB 12 Figure 6. Layer 1 Preliminary Rev. 0.2 ...
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Figure 7. Layer 2—Ground Plane Preliminary Rev. 0.2 Si5315-EVB 13 ...
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Si5315-EVB 14 Figure 8. Layer 3 Preliminary Rev. 0.2 ...
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Figure 9. Layer 4 Preliminary Rev. 0.2 Si5315-EVB 15 ...
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Si5315-EVB 16 Figure 10. Layer 5, FILT_DUT_PWR Preliminary Rev. 0.2 ...
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Figure 11. Layer 6, Bottom Preliminary Rev. 0.2 Si5315-EVB 17 ...
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Si5315-EVB 18 Figure 12. Bottom Silkscreen Preliminary Rev. 0.2 ...
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Factory Default Configuration Table 6. Factory Default Jumper Settings The jumper settings in Table 6 result in the following: SFOUT = LVPECL outputs 19.44 MHz input clocks 155.52 MHz output clocks BW = 112 Hz DBL2_BY = CKOUT2 enabled ...
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Si5315-EVB N : OTES 20 Preliminary Rev. 0.2 ...
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... D C OCUMENT HANGE LIST Revision 0.1 to Revision 0.2 Removed Si5315-EVB from Appendix of Si5315- EVB, Si5316-EVB, Si5319-EVB, Si532/23-EVB, Si5325/26-EVB with Si5315-EVB Appendix B User’s Guide Revised Revision 0 stand-alone Si5315-EVB User’s Guide Preliminary Rev. 0.2 Si5315-EVB 21 ...
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