FPDXSDUR-43USB/NOPB National Semiconductor, FPDXSDUR-43USB/NOPB Datasheet

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FPDXSDUR-43USB/NOPB

Manufacturer Part Number
FPDXSDUR-43USB/NOPB
Description
KIT EVAL DS99R421 CONV TO LVDS
Manufacturer
National Semiconductor

Specifications of FPDXSDUR-43USB/NOPB

Main Purpose
Interface, Serializer, Deserializer (SERDES)
Utilized Ic / Part
DS90UR124, DS99R421
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Other names
FPDXSDUR-43USB
© 2009 National Semiconductor Corporation
5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II
LVDS (Embedded Clock DC-Balanced) Converter
General Description
The DS99R421 converts a FPD-Link input with 4 non-DC
Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-
sampled low speed control bits into a single LVDS DC-bal-
anced serial stream with embedded clock information. This
single serial stream simplifies transferring the 24-bit bus over
a single differential pair of PCB traces and cable by eliminat-
ing the skew problems between the 3 parallel LVDS data
inputs and LVDS clock paths. It saves system cost by nar-
rowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB
layers, cable width, connector size, and pins.
The DS99R421 incorporates a single serialized LVDS signal
on the high-speed I/O. Embedded clock LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the converter
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding is used to support AC-Coupled intercon-
nects.
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
300113
FIGURE 1. Block Diagram
DS99R421
Features
5 MHz–43 MHz embedded clock & DC-Balanced data
transmission (21 total LVDS data bits plus 3 low speed
LVCMOS data bits)
User adjustable pre-emphasis driving ability through
external resistor on LVDS outputs and capable to drive up
to 10 meters shielded twisted-pair cable
Supports AC-coupling data transmission
100Ω Integrated termination resistor at LVDS input
Power-down control
Available @SPEED BIST to DS90UR124 to validate link
integrity
All LVCMOS inputs & control pins have internal pulldown
Schmitt trigger inputs on OS[2:0] to minimize metastable
conditions.
Outputs Tri-Stated through DEN
On-chip filters for PLLs
Power supply range 3.3V ± 10%
Automotive temperature range −40°C to +105°C
Greater than 8kV ESD Tolerance
Meets ISO 10605 ESD and AEC-Q100 compliance
30011301
September 1, 2009
www.national.com

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FPDXSDUR-43USB/NOPB Summary of contents

Page 1

... In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC bal- anced encoding is used to support AC-Coupled intercon- nects. Block Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation DS99R421 Features ■ 5 MHz–43 MHz embedded clock & DC-Balanced data ...

Page 2

Application Overview www.national.com FIGURE 2. Typical Application Diagram 2 30011302 ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...

Page 4

Symbol Parameter V Output Differential Voltage OD (Figure 10) ΔV Output Differential Voltage OD Unbalance V Output Voltage Offset OS ΔV Output Voltage Offset OS Difference I Output Short Circuit OS Current I TRI-STATE Output Current PWDNB = 0V, OZ ...

Page 5

Input Timing Requirements for OS[2:0] Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter F [2:0] Maximum Frequency OS Limitation of OS[2:0] Input to Output Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. ...

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AC Timing Diagrams and Test Circuits FIGURE 4. Serializer LVDS Output Load and Transition Times www.national.com FIGURE 3. LVDS Input Checkerboard Pattern FIGURE 5. RxIN to DOUT Delay – RCTCD 6 30011306 30011307 30011308 ...

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FIGURE 6. Receiver LVDS Input Mapping FIGURE 7. Receiver RITOL Min and Max 7 30011309 30011310 www.national.com ...

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FIGURE 8. Receiver RITOL Left and Right FIGURE 9. Serializer Output Eye Opening FIGURE 10. Serializer V Diagram OD 8 30011311 30011312 30011313 ...

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Pin Descriptions Pin # Pin Name I/O/PWR FPD-LINK LVDS RECEIVER INPUT PINS 28, 30, 32 RxIN[2:0]− LVDS_I 29, 31, 33 RxIN[2:0]+ LVDS_I 34 RxCLKIN− LVDS_I 35 RxCLKIN+ LVDS_I OVER SAMPLED INPUT PINS 3-1 OS[2:0] LVCMOS_I CONTROL AND CONFIGURATION PINS 4 ...

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Pin # Pin Name I/O/PWR GND GND SER SER GND ...

Page 11

Functional Description The DS99R421 is a Video Interface converter. It converts an FPD-Link interface (3 LVDS data channels + 1 LVDS Clock, e.g. DS90C365A or equivalent) plus up to three (3) LVCMOS additional signals into a single high-speed LVDS serial ...

Page 12

The three over sampled bits are mapped to DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 = bit 23. If the OS bits are not required, internal pull-down will bias the input to a ...

Page 13

HIGH once a BER of 1x10 the transmission link. Applications Information USING THE DS99R421 AND DS90UR124 The DS99R421 allows a FPD-Link based bus to connect to a single-channel serial LVDS interface in a Display using the latest generation ...

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Functional Overview * Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC Balanced www.national.com FPD-Link LVDS Input Mapping (3 LVDS Data + 1 LVDS Clock) Single Serialized LVDS Bitstream* FIGURE 11. ...

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FIGURE 12. AC Coupled Application FIGURE 13. DS99R421 Typical Application Connection 15 30011314 30011316 www.national.com ...

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FIGURE 14. Receiver Termination Option 2 FIGURE 15. Receiver Termination Option 3 16 30011317 30011318 ...

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Physical Dimensions inches (millimeters) unless otherwise noted Ordering Information NSID DS99R421QSQ 36-Lead LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS99R421QSQX 36-Lead LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch, 2500 std reel DS99R421ISQ 36-Lead LLP, ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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