SI3000SSI-EVB Silicon Laboratories Inc, SI3000SSI-EVB Datasheet - Page 8
SI3000SSI-EVB
Manufacturer Part Number
SI3000SSI-EVB
Description
BOARD EVAL PARALLEL PORT SI3000
Manufacturer
Silicon Laboratories Inc
Specifications of SI3000SSI-EVB
Main Purpose
Audio, CODEC
Utilized Ic / Part
SI3000
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si3000
Table 7. Switching Characteristics—Serial Interface
(V
8
Parameter
Cycle Time, SCLK
SCLK Duty Cycle
Delay Time, SCLK to FSYNC
Delay Time, SCLK to SDO Valid
Delay Time, SCLK to FSYNC
Setup Time, SDI, before SCLK
Hold Time, SDI, after SCLK
Setup Time, FSYNC (mode 2) before
MCLK
Hold Time, FSYNC (mode 2) after
MCLK
Note: All timing is referenced to the 50% level of the waveform. Input test levels are V
A
FSYNC
(mode 0)
FSYNC
(mode 1)
FSYNC
(mode 2)
SDO
SDI
SCLK
16 Bit
16 Bit
, V
D
= 5 V ±5% or 3.3 V ±10%, T
High-Z
t
d3
A
Figure 2. Serial Interface Timing Diagram
= 0 to 70°C, C
D15
D15
t
d1
t
su
Symbol
t
c
t
t
t
t
t
t
t
dty
t
t
d1
d2
d3
su
su
h
h
c
L
= 20 pF)
D14
D14
Rev. 1.4
Test Condition
t
h
... D2
... D2
t
d2
D1
D1
Min
354
25
20
25
20
—
—
—
—
IH
= V
1/256 Fs
D
D0
– 0.4 V, V
D0
Typ
D0
50
—
—
—
—
—
—
—
IL
= 0.4 V
Max
t
d3
10
20
10
High-Z
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
V
V
OH
OL