EVB9303 SMSC, EVB9303 Datasheet - Page 7

• Manufacturer Part Number: EVB9303
• Description: EVALUATION BOARD FOR LAN9303
• Manufacturer: SMSC

Specifications of EVB9303

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9303
• Primary Attributes: 3 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: Full Duplex and HP Auto-MDIX Support, 10BASE-T and 100BASE-TX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1095

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.2.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.2.4 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.2.5 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.2.6 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.2.7 Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.3
13.3.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.3.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.4
13.4.1 General Switch CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
13.4.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SMSC LAN9303/LAN9303i
13.2.2.2
13.2.2.3
13.2.2.4
13.2.3.1
13.2.3.2
13.2.4.1
13.2.4.2
13.2.4.3
13.2.4.4
13.2.4.5
13.2.4.6
13.2.4.7
13.2.4.8
13.2.5.1
13.2.5.2
13.2.6.1
13.2.6.2
13.2.6.3
13.2.6.4
13.2.6.5
13.2.6.6
13.2.6.7
13.2.6.8
13.2.7.1
13.2.7.2
13.2.7.3
13.2.7.4
13.2.7.5
13.2.7.6
13.2.7.7
13.3.2.1
13.3.2.2
13.3.2.3
13.3.2.4
13.3.2.5
13.3.2.6
13.3.2.7
13.3.2.8
13.3.2.9
13.3.2.10
13.3.2.11
13.3.2.12
13.3.2.13
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
13.4.2.5
13.4.2.6
13.4.2.7
13.4.2.8
13.4.2.9
13.4.2.10
13.4.2.11
13.4.2.12
13.4.2.13
13.4.2.14
13.4.2.15
13.4.2.16
13.4.2.17
13.4.2.18
13.4.2.19
Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) ........................................................................................................... 145
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)...................................................................................... 146
LED Configuration Register (LED_CFG) ...................................................................................................................................................... 147
EEPROM Command Register (E2P_CMD) .................................................................................................................................................. 148
EEPROM Data Register (E2P_DATA).......................................................................................................................................................... 151
Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... 152
Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... 154
Port 0 Manual Flow Control Register (MANUAL_FC_0)............................................................................................................................... 156
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... 158
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... 159
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ 161
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... 162
Switch Fabric CSR Interface Direct Data Registers (SWITCH_CSR_DIRECT_DATA) ............................................................................... 164
PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. 167
PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... 168
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... 170
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... 172
Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... 174
Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ 175
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... 176
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. 178
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... 181
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. 182
Chip ID and Revision (ID_REV).................................................................................................................................................................... 184
Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... 185
Hardware Configuration Register (HW_CFG)............................................................................................................................................... 186
General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... 187
General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... 188
Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 189
Reset Control Register (RESET_CTL) ......................................................................................................................................................... 190
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) ................................................................................................................ 193
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ..................................................................................................................... 195
Port x PHY Identification MSB Register (PHY_ID_MSB_x).......................................................................................................................... 197
Port x PHY Identification LSB Register (PHY_ID_LSB_x)............................................................................................................................ 198
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) ................................................................................................... 199
Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) ................................................. 202
Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) ......................................................................................................... 204
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)..................................................................................... 205
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) .............................................................................................................. 206
Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) .......................................................... 207
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)........................................................................................... 209
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) ............................................................................................................ 210
Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x).............................................................................. 211
Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... 223
Switch Reset Register (SW_RESET) ........................................................................................................................................................... 224
Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ 225
Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... 226
Port x MAC Version ID Register (MAC_VER_ID_x) ..................................................................................................................................... 227
Port x MAC Receive Configuration Register (MAC_RX_CFG_x) ................................................................................................................. 228
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) ........................................................................................... 229
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x).......................................................................................................... 230
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)................................................................................ 231
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)............................................................................ 232
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)............................................................................ 233
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)........................................................................ 234
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) ..................................................................... 235
Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) ............................................................................................. 236
Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)......................................................................................................... 237
Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x).......................................................................................... 238
Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) ............................................................................................. 239
Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) ........................................................................................... 240
Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) ........................................................................................ 241
Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ 242
Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) ............................................................................................. 243
Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... 244
Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) ..................................................................................... 245
DATASHEET
7
Revision 1.4 (07-07-10)