AD9516-3/PCBZ Analog Devices Inc, AD9516-3/PCBZ Datasheet - Page 52

• Manufacturer Part Number: AD9516-3/PCBZ
• Description: BOARD EVAL FOR AD9516-3 2.0GHZ
• Manufacturer: Analog Devices Inc

Specifications of AD9516-3/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-3
• Primary Attributes: 2 Inputs, 14 Outputs, 2GHz VCO
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9516-0, AD9516-1, AD9516-2
• Silicon Family Name: AD9516-X
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-3
Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDO
CS
CS
CS
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON’T CARE
SCLK
SDIO
CS
DON’T CARE
R/W
I14
W1
DON'T CARE
DON'T CARE
W1
R/W
A0 A1 A2 A3
W0
W1
16-BIT INSTRUCTION HEADER
A12
I13
W0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W0
A12
t
S
R/W
I12
A12 = 0
A11 A10 A9 A8 A7
A4
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
t
A5 A6 A7 A8
DS
Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
W1
Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
SCLK
SDIO
W0
SDO
I11
A11 = 0
t
DH
CS
Figure 67. Timing Diagram for Serial Control Port Register Read
A12
A6 A5
A9 A10 A11 A12
A11
I10
A10 = 0
t
HI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
DATA BIT N
A10
t
LO
W0
t
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DV
A9
I9
A9
A1 A0
t
W1
CLK
R/W
A8
I8
A8
D0
D7 D6 D5 D4 D3
DATA BIT N – 1
REGISTER (N – 1) DATA
A7
D1
I7
A7
REGISTER (N) DATA
REGISTER (N) DATA
D2 D3 D4
A6
I6
A6
A5
D2 D1 D0 D7
D5 D6 D7
I5
A5
D4
REGISTER (N – 2) DATA
D3
I4
A4
D0
D2
D6 D5
REGISTER (N – 1) DATA
D1 D2
REGISTER (N + 1) DATA
I3
A3
D1
I2
A2
D4 D3 D2
D3 D4 D5
REGISTER (N – 3) DATA
D0
t
I1
A1
C
D1 D0
D6
DON'T CARE
DON'T CARE
LSB
I0
A0
D7
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON’T CARE
DON’T
CARE