LMZ14203TZ-ADJ/NOPB National Semiconductor, LMZ14203TZ-ADJ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LMZ14203TZ-ADJ/NOPB
• Description: IC BUCK SYNC ADJ 3A TO-PMOD-7
• Manufacturer: National Semiconductor
• Series: SIMPLE SWITCHER®r
• Type: Point of Load (POL) Non-Isolated with UVLOr

Specifications of LMZ14203TZ-ADJ/NOPB

• Output: 0.8 ~ 6 V
• Number Of Outputs: 1
• Power (watts): 18W
• Mounting Type: Surface Mount
• Voltage - Input: 6 ~ 42 V
• Package / Case: TO-PMOD-7, Power Module
• 1st Output: 0.8 ~ 6 VDC @ 3A
• Size / Dimension: 0.40" L x 0.54" W x 0.18" H (10.16mm x 13.77mm x 4.57mm)
• Power (watts) - Rated: 18W
• Operating Temperature: -40°C ~ 125°C
• Efficiency: 90%
• Approvals: EN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -
• Other names: LMZ14203TZ-ADJTR

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in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will
cause observable high frequency noise on the output pin if
the input capacitor (Cin1) is placed at a distance away from
the LMZ14203. Therefore place C
the LMZ14203 VIN and GND exposed pad. This will minimize
the high di/dt area and reduce radiated EMI. Additionally,
grounding for both the input and output capacitor should con-
sist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
capacitor C
the FB node is high impedance, maintain the copper area as
small as possible. The trace are from R
should be routed away from the body of the LMZ14203 to
minimize noise.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
ground planes. For best results use a 6 x 6 via array with
minimum via diameter of 10mils (254 μm) thermal vias spaced
59mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
FF
, should be located close to the FB pin. Since
FBT
and R
IN1
FBB
as close as possible to
, and the feed forward
FBT
, R
FBB
, and C
30107011
FF
12
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference.
If FB rises above 0.92V the on-time is immediately terminat-
ed. This condition is known as over-voltage protection (OVP).
It can occur if the input voltage is increased very suddenly or
if the output load is decreased very suddenly. Once OVP is
activated, the top MOSFET on-times will be inhibited until the
condition clears. Additionally, the synchronous MOSFET will
remain on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by
monitoring the current in the synchronous MOSFET. Refer-
ring to the Functional Block Diagram, when the top MOSFET
is turned off, the inductor current flows through the load, the
PGND pin and the internal synchronous MOSFET. If this cur-
rent exceeds 4.2A (typical) the current limit comparator dis-
ables the start of the next on-time period. The next switching
cycle will occur only if the FB input is less than 0.8V and the
inductor current has decreased below 4.2A. Inductor current
is monitored during the period of time the synchronous MOS-
FET is conducting. So long as inductor current exceeds 4.2A,
further on-time intervals for the top MOSFET will not occur.
Switching frequency is lower during current limit due to the
longer off-time. It should also be noted that current limit is
dependent on both duty cycle and temperature.
THERMAL PROTECTION
The junction temperature of the LMZ14203 should not be al-
lowed to exceed its maximum ratings. Thermal protection is
implemented by an internal Thermal Shutdown circuit which
activates at 165 °C (typ) causing the device to enter a low
power standby state. In this state the main MOSFET remains
off causing V
discharged to ground. Thermal protection helps prevent
catastrophic failures for accidental device overheating. When
the junction temperature falls back below 145 °C (typ Hyst =
20 °C) the SS pin is released, V
operation resumes.
Applications requiring maximum output current especially
those at high input voltage may require application derating
at elevated temperatures.
ZERO COIL CURRENT DETECTION
The current of the lower (synchronous) MOSFET is monitored
by a zero coil current detection circuit which inhibits the syn-
chronous MOSFET when its current reaches zero until the
next on-time. This circuit enables the DCM operating mode,
which improves efficiency at light loads.
O
to fall, and additionally the CSS capacitor is
O
rises smoothly, and normal