LMZ14202TZ-ADJ/NOPB National Semiconductor, LMZ14202TZ-ADJ/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMZ14202TZ-ADJ/NOPB
• Description: IC BUCK SYNC ADJ 2A TO-PMOD-7
• Manufacturer: National Semiconductor
• Series: SIMPLE SWITCHER®r
• Type: Point of Load (POL) Non-Isolated with UVLOr

Specifications of LMZ14202TZ-ADJ/NOPB

• Output: 0.8 ~ 6 V
• Number Of Outputs: 1
• Power (watts): 12W
• Mounting Type: Surface Mount
• Voltage - Input: 6 ~ 42 V
• Package / Case: TO-PMOD-7, Power Module
• 1st Output: 0.8 ~ 6 VDC @ 2A
• Size / Dimension: 0.40" L x 0.54" W x 0.18" H (10.16mm x 13.77mm x 4.57mm)
• Power (watts) - Rated: 12W
• Operating Temperature: -40°C ~ 125°C
• Efficiency: 90%
• Approvals: EN
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 7
• Mounting: Surface Mount
• Case Length: 10.16mm
• Case Height: 4.57mm
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -
• Lead Free Status / Rohs Status: Compliant
• Other names: LMZ14202TZ-ADJTR

Given the typical thermal resistance from junction to case to
be 1.9 °C/W. Use the 85°C power dissipation curves in the
Typical Performance Characteristics section to estimate the
P
it is 1.5W.
θ
To reach θ
effectively. With no airflow and no external heat, a good esti-
mate of the required board area covered by 1 oz. copper on
both the top and bottom metal layers is:
Board Area_cm
As a result, approximately 20.2 square cm of 1 oz copper on
top and bottom layers is required for the PCB design. The
PCB copper heat sink must be connected to the exposed pad.
Approximately thirty six, 10mils (254 μm) thermal vias spaced
59mils (1.5 mm) apart must connect the top copper to the
bottom copper. For an example of a high thermal performance
PCB layout, refer to the Evaluation Board application note
AN-2024.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will
cause observable high frequency noise on the output pin if
the input capacitor (Cin1) is placed at a distance away from
the LMZ14202. Therefore place C
the LMZ14202 VIN and GND exposed pad. This will minimize
the high di/dt area and reduce radiated EMI. Additionally,
grounding for both the input and output capacitor should con-
sist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
capacitor C
CA
IC-LOSS
= (125 — 85) / 1.5W — 1.9) = 24.8
for the application being designed. In this application
CA
FF
, should be located close to the FB pin. Since
= 24.8, the PCB is required to dissipate heat
2
= 500°C x cm
FBT
and R
2
/W / θ
IN1
FBB
as close as possible to
JC
, and the feed forward
(19)
30114511
13
the FB node is high impedance, maintain the copper area as
small as possible. The trace are from R
should be routed away from the body of the LMZ14202 to
minimize noise.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
ground planes. For best results use a 6 x 6 via array with
minimum via diameter of 10mils (254 μm) thermal vias spaced
59mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
FBT
, R
FBB
www.national.com
, and C
FF