LTM4607EV#PBF Linear Technology, LTM4607EV#PBF Datasheet - Page 20

IC BUCK/BOOST SYNC ADJ 5A 141LGA

LTM4607EV#PBF

Manufacturer Part Number
LTM4607EV#PBF
Description
IC BUCK/BOOST SYNC ADJ 5A 141LGA
Manufacturer
Linear Technology
Series
µModuler
Type
Point of Load (POL) Non-Isolatedr
Datasheet

Specifications of LTM4607EV#PBF

Design Resources
LTM4607 Spice Model
Output
0.8 ~ 24 V
Number Of Outputs
1
Power (watts)
120W
Mounting Type
Surface Mount
Voltage - Input
4.5 ~ 36 V
Package / Case
141-LGA
1st Output
0.8 ~ 24 VDC @ 5A
Size / Dimension
0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
Power (watts) - Rated
120W
Operating Temperature
-40°C ~ 85°C
Efficiency
98%
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3rd Output
-
2nd Output
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTM4607EV#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTM4607EV#PBF@@
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS INFORMATION
LTM4607
Layout Checklist/Example
The high integration of LTM4607 makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current path, includ-
• Place high frequency input and output ceramic capaci-
• Route SENSE
20
ing V
minimize the PCB conduction loss and thermal stress.
tors next to the V
high frequency noise
PC trace spacing. Avoid sense lines passing through
noisy areas, such as switch nodes.
IN
, R
SENSE
and SENSE
, SW1, SW2, PGND and V
IN
, PGND and V
+
leads together with minimum
SW1
V
PGND
OUT
C
OUT
OUT
pins to minimize
OUT
Figure 15. Recommended PCB Layout
. It helps to
KELVIN CONNECTIONS TO R
+ –
L1
R
SENSE
SGND
SW2
• Place a dedicated power ground layer underneath the
• To minimize the via conduction loss and reduce module
• Do not put vias directly on pads, unless the vias are
• Use a separated SGND ground copper area for com-
Figure 15. gives a good example of the recommended
layout.
unit.
thermal stress, use multiple vias for interconnection
between the top layer and other power layers
capped.
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
V
SENSE
IN
R
SENSE
PGND
C
IN
4607 F15
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