HCMS-3904 Avago Technologies US Inc., HCMS-3904 Datasheet - Page 14

LED DISPLAY 5X7 4CHAR 3.8MM ORN

HCMS-3904

Manufacturer Part Number
HCMS-3904
Description
LED DISPLAY 5X7 4CHAR 3.8MM ORN
Manufacturer
Avago Technologies US Inc.
Series
HCMS-39xxr
Datasheet

Specifications of HCMS-3904

Millicandela Rating
*
Internal Connection
*
Size / Dimension
*
Color
Orange
Configuration
*
Voltage - Forward (vf) Typ
*
Package / Case
12-DIP
Display Type
Alphanumeric
Number Of Digits/alpha
4
Digit/alpha Size
0.15" (3.8mm)
Character Format
Dot Matrix
Character Size
3.81mm
Led Color
Orange
Luminous Intensity
128µcd
No. Of Digits / Alpha
4
Display Area Width
17.78mm
Display Area Height
10.16mm
Number Of Digits
4
Illumination Color
Orange
Wavelength
588 nm
Operating Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Common Pin
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HCMS-3904
Manufacturer:
Avago Technologies
Quantity:
135
Part Number:
HCMS-3904
Manufacturer:
AVAGO/安华高
Quantity:
20 000
Serial/Simultaneous Data Output D
Bit D
D
Control Register writes. The default mode (logic low) is
the serial D
to the last bit (D
Storing logic high to bit D
simultaneous mode, which affects the Control Register
only. In simultaneous mode, D
to D
Control Registers written to simultaneously. For example,
for n ICs in the serial mode, n * 8 clock pulses are needed
to load the same data in all Control Registers. In the
simultaneous mode, n ICs only need 8 clock pulses to
load the same data in all Control Registers. The propaga-
tion delay from the first IC to the last is n * t
External Oscillator Prescaler Bit D
Bit D
an external Display Oscillator. When this bit is logic low,
the external Display Oscillator directly sets the internal
display clock rate. When this bit is logic high, the external
oscillator is divided by 8. This scaled frequency then sets
the internal display clock rate. It takes 512 cycles of the
display clock (or 8 x 512 = 4096 cycles of an external clock
with the divide by 8 prescaler) to completely refresh the
display once. Using the prescaler bit allows the designer
to use a higher external oscillator frequency without
extra circuitry.
This bit has no affect on the internal Display Oscillator
Frequency.
14
OUT
IN
1
0
between serial and simultaneous data entry during
. This arrange ment allows multiple ICs to have their
of Control Word 1 is used to scale the frequency of
of control word 1 is used to switch the mode of
OUT
mode. In serial mode, D
7
) of the Control Shift Register.
OUT
0
1
is logically connected
0
changes D
OUT
DOUTP
is connected
OUT
.
to
Bits D
These bits must always be pro-grammed to logic low.
Cascaded ICs
Figure 8 shows how two ICs are connected within an
HCMS-39XX display. The first IC controls the four left-
most characters and the second IC controls the four
right-most characters. The Dot Registers are connected
in series to form a 320-bit dot shift register. The location
of pixel 0 has not changed. However, Dot Shift Register
bit 0 of IC2 becomes bit 160 of the 320-bit dot shift
register.
The Control Registers of the two ICs are independent
of each other. This means that to adjust the display
brightness the same control word must be entered
into both ICs, unless the Control Registers are set to
simultaneous mode.
Longer character string systems can be built by cascading
multiple displays together. This is accom plished by
creating a five-line bus. This bus consists of CE, RS, BL,
Reset, and CLK. The display pins are connected to the
corresponding bus line. Thus, all CE pins are connected
to the CE bus line. Similarly, bus lines for RS, BL, Reset,
and CLK are created. Then D
most display. D
next display. The left-most display receives its D
the D
most display is not used.
Each display may be set to use its internal oscillator, or
the displays may be synchronized by setting up one
display as the master and the others as slaves. The slaves
are set to receive their oscillator input from the master’s
oscillator output.
OUT
2
-D
6
of the display to its right. D
OUT
from this display is connected to the
IN
is connected to the right-
OUT
from the left-
IN
from

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