IDT72T55248L5BB IDT, Integrated Device Technology Inc, IDT72T55248L5BB Datasheet

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IDT72T55248L5BB

Manufacturer Part Number
IDT72T55248L5BB
Description
IC CTRL QUADMUX FLOW 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72T55248L5BB

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T55248L5BB
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAMS
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Choose from among the following memory organizations:
IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential
Queues total
IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential
Queues total
IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential
Queues total
User Selectable Mux / Demux / Broadcast Write Modes
Mux Mode offers 4:1 architecture
- Five discrete clock domains, four write clocks and one read clock
- Four separate write ports, writes data to four independent Queues
- One single read port, capable of reading from any four Queues
- Selectable single or double data rate (SDR/DDR) on read and write
- 10-bit wide write ports in single data rate, doubles internally in double
- 40-bit wide read port, doubles internally in double data rate,
- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)
- Fully independent status flags for every Queue
- Composite Empty/Output Ready Flag monitors currently selected
- Dedicated partial reset for every Queue
ports
data rate
selectable between the four independent Queues
Queue
Queue 3
Data In
Queue 1
Data In
Queue 2
Data In
Queue 0
Data In
D[19:10]
D[29:20]
D[39:30]
FF2/ IR2
D[9:0]
WCLK2
FF0/IR0
FF1/IR1
FF3/IR3
WCLK0
WCLK1
WCLK3
WEN0
WCS0
WEN1
WCS1
WEN2
WCS2
WEN3
WCS3
PAF0
PAF1
PAF2
PAF3
10
10
10
10
2.5V QUADMUX DDR FLOW-CONTROL DEVICE
WITH MUX/DEMUX/BROADCAST FUNCTIONS
8,192 x 40 x 4
16,384 x 40 x 4
32,768 x 40 x 4
Mux Mode
32,768 x 40
32,768 x 40
32,768 x 40
16,384 x40
16,384 x40
32,768 x 40
16,384 x40
16,384 x40
8,192 x 40
8,192 x 40
8,192 x 40
8,192 x 40
1
Queue 2
Queue 3
Queue 0
Queue 1
• • • • •
• • • • •
Demux Mode offers 1:4 architecture
- Five discrete clock domains, one write clock and four read clocks
- Four separate read ports, read data from four independent Queues
- One single write port, capable of writing to any four Queues
- Selectable single or double data rate on read and write ports
- 10-bit wide read ports in single data rate, doubles internally in double
- 40-bit wide write port, doubles internally in double data rate,
- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)
- Fully independent status flags for every Queue
- Composite Full/Input Ready Flag monitors currently selected Queue
- Dedicated partial reset for every Queue
Broadcast Write Mode offers, 1:4 architecture (with simultaneous
writes to all Queues)
- Five discrete clock domains, one write clock and four read clocks
- Four separate read ports, read data from four independent Queues
- One single write port, writes to all four independent Queues
- 10-bit wide read ports in single data rate, doubles internally in double
- 40-bit wide write port, doubles internally in double data rate
- Selectable single or double data rate on read and write ports
- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)
data rate
selectable between the four independent Queues
simultaneously
data rate
(See next pages for Demux and Broadcast modes)
6157 drw01
x10,x20,x40
Q[39:0]
2
CEF/COR
EF0/OR0
PAE0
EF1/OR1
PAE1
EF2/OR2
PAE2
EF3/OR3
PAE3
RCLK0
REN0
RCS0
OE0
OS[1:0]
FEBRUARY 2009
Data Out
IDT72T55248
IDT72T55258
IDT72T55268
DSC-6157/5

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IDT72T55248L5BB Summary of contents

Page 1

FEATURES • • • • • Choose from among the following memory organizations: IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential Queues total IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential Queues total IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Features ...................................................................................................................................................................................................................... 1,4 Description ...................................................................................................................................................................................................................... 6 Pin Configuration ............................................................................................................................................................................................................. 8 Pin Descriptions .......................................................................................................................................................................................................... 9-13 Device ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Figure 1. QuadMux Block Diagram .................................................................................................................................................................................. 7 Figure 2a. AC Test Load ................................................................................................................................................................................................ 18 Figure ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K FEATURES (CONTINUED) - Fully independent status flags for every Queue - Composite Full/Input Ready Flag ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K FUNCTIONAL BLOCK DIAGRAMS (CONTINUED) Broadcast Mode WCLK0 WEN0 WCS0 D[39:0] Data In x10,x20,x40 FF0/ IR0 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K DESCRIPTION The IDT72T55248/72T55258/72T55268 QuadMux flow-control devices are ideal for many applications where data stream convergence ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WDDR WEN0 Write Control WCS0 Logic WCLK0 RDDR REN0 Read Control Logic RCS0 RCLK0 PAF0 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN CONFIGURATION A1 BALL PAD CORNER A MRS VREF ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN DESCRIPTIONS Symbol & Name I/O TYPE Pin No. CEF/COR Composite Empty/ HSTL-LVTTL If Mux ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. IW[1:0] Input Width CMOS (IW1-C12 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. Q[39:0] Data Output Bus HSTL-LVTTL ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. TCK (3) JTAG Clock HSTL-LVTTL ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. V +2.5V Supply Power CC ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K QUADMUX I/O USAGE SUMMARY SET-UP, CONFIGURATION & RESET PINS Regardless of the mode of operation, ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K ELECTRICAL CHARACTERISTICS (Industrial 2.5V ± 0.125V -40°C to +85°C) CC ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.15V 0°C to +70°C;Industrial: V ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K OUTPUT ENABLE & DISABLE TIMING OE Single Output V /2 Normally DDQ LOW Single Output ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K FUNCTIONAL DESCRIPTION MASTER RESET & DEVICE CONFIGURATION - MRS During Master Reset the device operation ...

Page 21

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K reset will determine the value. Table 1 lists the four offset values and how to ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K the instructional register to the offset read command (Hex Value = 0x0007). The TDO of ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K the Queue is full, the first read operation will cause HIGH ...

Page 24

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K HSTL/LVTTL I/O The inputs and outputs of this device can be configured for either LVTTL ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K MUX MODE BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: OS1 OS0 OW1 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K DEMUX MODE BYTE ORDER ON INPUT PORT: IS1 IS0 IW1 IW0 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K BROADCAST MODE BYTE ORDER ON INPUT PORT: IW1 IW0 H L BYTE ORDER ON INPUT ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K SELECTABLE MODES The device is capable of operating in three different modes, Mux, Demux, and ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K corresponding read clock, read enable, and read chip select. A data word will be read ...

Page 30

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K SIGNAL DESCRIPTIONS INPUTS: DATA INPUT BUS (D[39:0]) The data input bus can be 40, 20, ...

Page 31

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Data setup and hold times must be met with respect to the LOW-to-HIGH (and HIGH-to-LOW ...

Page 32

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K ing RCLK will enable the output bus. When the read chip select goes HIGH, the ...

Page 33

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K (FWFT/SI) and serial clock (SCLK) when programming the offset registers. When the serial write enable ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K prevent data overflow in the FWFT mode, the input ready flag of each Queue ...

Page 35

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K ECHO READ CLOCK (ERCLK0/1/2/3) There are four echo read clock outputs available in this device, ...

Page 36

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K TCK TDI/ TMS t TDO t 4 TRST t 3 SYSTEM INTERFACE PARAMETERS ...

Page 37

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K JTAG TIMING SPECIFICATIONS (IEEE 1149.1 COMPLIANT) The JTAG test port in this device is fully ...

Page 38

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Input is 0 TMS NOTES: 1. Five consecutive 1's at TMS will reset the ...

Page 39

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K THE INSTRUCTION REGISTER The instruction register (IR) is eight bits long and tells the device ...

Page 40

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K CLAMP The optional CLAMP instruction sets the outputs of an device to logic levels determined ...

Page 41

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K MRS t RSS WEN REN t RSS SWEN, SREN t RSS (4) IS[1:0] , (4) ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K RCLK0 PRS0/1 (1) PRS2/3 (1) t RSS WEN0/1, REN0/1 t RSS WEN2/3, REN2/3 t ENS ...

Page 43

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 PRS0/1 (1) PRS2/3 (1) t RSS WEN0, REN0/1 t RSS REN2 IS[1:0] ...

Page 44

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 PRS0/1/2/3 t RSS REN (2) 0/1/2/3 t RSS WEN0 EF/OR0/1/2/3 FF/IR0/1/2/3 CFF/CIR PAE0/1/2/3 PAF0/1/2/3 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 45 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 t ENS WEN0 Din[9:0] Word D-1 Word D ...

Page 47

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 WEN0 ENS ENH ENH IS[1: Queue ...

Page 48

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 t ENS WEN0 Din[9:0] Word 1 Word 2 ...

Page 49

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 49 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 50

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 50 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 51

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 51 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 52

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 WEN0 Din[9: WFF IR0 RCLK1 REN1 Q[19:10] ...

Page 53

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 t t ENS ENH WEN0 D[9: WFF IR0 RCLK0 REN0 Q[9:0] ...

Page 54

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K RCLK1 t ENS REN1 Q[19:10] Previous Data in Output Register EF1 RCLK0 t ENS REN0 ...

Page 55

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 55 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 56

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K RCLK0 t ENS REN0 OS[1: Queue (3) Q[39:0] Word Queue ...

Page 57

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 t ENS WEN0 IS[1: Queue ...

Page 58

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 58 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 59

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 t ENS WEN0 D[9:0] n+1 n+2 ...

Page 60

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K RCLK0 t ERCLK ERCLK0 REN0 t ENS RCS0 t CLKEN EREN0 EF0 ...

Page 61

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K COMMERCIAL AND INDUSTRIAL 61 TEMPERATURE RANGES FEBRUARY 01, 2009 ...

Page 62

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K CLKL CLKL WCLK t t ENS ENH WEN0 t PAFS PAF0 (1) D ...

Page 63

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK0 WEN0 PAF0 words in Queue RCLK0 REN0 NOTES: 1. ...

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K WCLK WEN D[39:0] D10 D11 ...

Page 65

ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package DATASHEET DOCUMENT HISTORY 12/01/2003 pgs 17, and 36. 03/22/2005 pgs 15-18, 21-24, 32, 34, and 65. 02/01/2009 pg. 65. CORPORATE HEADQUARTERS 6024 Silver Creek Valley ...

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