IDT72V51233L7-5BB IDT, Integrated Device Technology Inc, IDT72V51233L7-5BB Datasheet - Page 16

• Manufacturer Part Number: IDT72V51233L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51233L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51233L7-5BB

FUNCTIONAL DESCRIPTION
MASTER RESET
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programming either serially by the user via
the serial port, or using the default settings. During a master reset the state of
the following inputs determine the functionality of the part, these pins should be
held HIGH or LOW.
serially or via the default method before any read/write operations can begin.
PARTIAL RESET
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK
cycles before the PRS goes LOW. The partial reset is then performed by toggling
the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least
one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
partial reset will not effect the overall configuration and setup of the multi-queue
device and its queues.
SERIAL PROGRAMMING
ing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the PAF/PAE flags within
respective queues. All user programming is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and PAE/PAF offset values. The
IDT72V51233/72V51243/72V51253 devices are capable of up to 4 queues
and therefore contain 4 sets of registers for the setup of each queue.
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate
a serial bit stream which should be serially loaded into the device via the serial
port. For the IDT72V51233/72V51243/72V51253 devices the serial program-
ming requires a total number of serially loaded bits per device, (SCLK cycles with
SENI enabled), calculated by: 19+(Qx72) where Q is the number of queues the
user wishes to setup within the device. Please refer to the separate Application
Note, AN-303 for recommended control of the serial programming port.
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable), is LOW. Once serial programming of the device has been successfully
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
A Master Reset is performed by toggling the MRS input from HIGH to LOW
FM – Flag bus Mode
IW, OW – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM – Programming mode, serial or default
DF – Offset value for PAE and PAF
Once a master reset has taken place, the device must be programmed either
See Figure 4, Master Reset for relevant timing.
A Partial Reset is a means by which the user can reset both the read and write
A Partial Reset only resets the read and write pointers of a given queue, a
See Figure 5, Partial Reset for relevant timing.
The multi-queue flow-control device is a fully programmable device, provid-
During a Master Reset if the DFM (Default Mode) input is LOW, then the device
Once the master reset is complete and MRS is HIGH, the device can be
16
completed the device will indicate this via the SENO (serial output enable) going
active, LOW. Upon detection of completion of programming, the user should
cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI
once programming of a device is complete. Therefore, SENO will go LOW after
programming provided SENI is LOW, once SENI is taken HIGH again, SENO
will also go HIGH. The operation of the SO output is similar, when programming
of a given device is complete, the SO output will follow the SI input.
be cascaded. The user can load all devices via the serial input port control pins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
program to generate the serial bit stream, the program prompting the user for
the number of devices to be programmed. The SENO and SO (serial out) of
the first device should be connected to the SENI and SI inputs of the second
device respectively and so on, with the SENO & SO outputs connecting to the
SENI & SI inputs of all devices through the chain. All devices in the chain should
be connected to a common SCLK. The serial output port of the final device should
be monitored by the user. When SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully com-
pleted. Upon detection of completion of programming, the user should cease all
programming and take SENI of the first device in the chain inactive, HIGH.
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream. When programming of this device is complete it will take
its SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its SENI
input LOW. This process continues through the chain until all devices are
programmed and the SENO of the final device goes LOW.
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72V51233/72V51243/72V51253 de-
vices require a total number of serially loaded bits per device to complete serial
programming, (SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)]
where Q is the number of queues the user wishes to setup within the device,
where n is the number of devices in the chain.
connection and timing information.
DEFAULT PROGRAMMING
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means by which to setup the multi-queue flow-control device,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possible are setup, with all of the parts available memory blocks being allocated
equally between the queues. The values of the PAE/PAF offsets is determined
by the state of the DF (default) pin during a master reset.
setup 4 queues, each queue configured as follows: For the IDT72V51233 with
x9 input and x9 output ports, 16,384 x 9. If one or both ports is x18, 8,192 x
18. For the IDT72V51243 with x9 input and x9 output ports, 32,768 x 9. If one
or both ports is x18, 16,384 x 18. For the IDT72V51253 with x9 input and x9
output ports, 65,536 x 9. If one or both ports is x18, 32,768 x 18. For both devices
the value of the PAE/PAF offsets is determined at master reset by the state of
the DF input. If DF is LOW then both the PAE & PAF offset will be 8, if HIGH then
the value is 128.
If devices are being used in expansion mode the serial ports of devices should
As mentioned, the first device in the chain has its serial input port controlled
Once all serial programming has been successfully completed, normal
See Figure 6, Serial Port Connection and Figure 7, Serial Programming for
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
For the IDT72V51233/72V51243/72V51253 devices the default mode will
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES