IDT89HPES16T4G2ZABX8 IDT, Integrated Device Technology Inc, IDT89HPES16T4G2ZABX8 Datasheet - Page 7

• Manufacturer Part Number: IDT89HPES16T4G2ZABX8
• Description: IC PCI SW 16LANE 4PORT 288-SBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4G2ZABX8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T4G2ZABX8

IDT 89HPES16T4G2 Data Sheet
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
V
REFRES0
REFRES2
REFRES4
REFRES6
V
V
Signal
Signal
V
DD
V
DD
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
Type
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
Table 7 Power, Ground, and SerDes Resistor Pins
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Port 6 External Reference Resistor. Provides a reference for the Port 6
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
DD.
DD.
LVTTL I/O buffer power supply.
Table 6 Test Pins
Power supply for core logic.
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Name/Description
Name/Description
September 13, 2010