IDT72V51333L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51333L7-5BB8 Datasheet - Page 20

• Manufacturer Part Number: IDT72V51333L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51333L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 18b
• Organization: 4Kx18x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51333L7-5BB8

within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
empty status, when a queue is selected on the read port, this status is output via
the PAE flag. The PAE flag value for each queue is programmed during multi-
queue device programming (along with the number of queues, queue depths
and almost full values). The PAE offset value, n, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAE value of different queues within the same device
can be different values.
will switch to the new queue and provide the user with the new queue status,
on the second cycle after a new queue selection is made, on the same RCLK
cycle that data actually falls through to the output register from the new queue.
That is, a new queue can be selected on the read port via the RDADD bus,
RADEN enable and a rising edge of RCLK. On the second rising edge of RCLK
following a queue selection, the data word from the new queue will be available
at the output register and the PAE flag output will show the empty status of the
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
As mentioned, every queue within a multi-queue device has its own almost
When queue switches are being made on the read port, the PAE flag output
20
newly selected queue. The PAE is flag output is double register buffered, so
when a read operation occurs at the almost empty boundary causing the
selected queue status to go almost empty the PAE will go LOW 2 RCLK cycles
after the read. The same is true when a write occurs, there will be a 2 RCLK
cycle delay after the write operation.
occur based on a rising edge of RCLK. Internally the multi-queue device
monitors and keeps a record of the almost empty status for all queues. It is possible
that the status of a PAE flag maybe changing internally even though that flag is
not the active queue flag (selected on the read port). A queue selected on the
write port may experience a change of its internal almost empty flag status based
on write operations. The multi-queue flow-control device also provides a
duplicate of the PAE flag on the PAE[3:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
So the PAE flag delays are:
from a read operation to PAE flag LOW is 2 RCLK + t
The delay from a write operation to PAE flag HIGH is t
Note, if t
The PAE flag is synchronous to the RCLK and all transitions of the PAE flag
See Figures 20 and 21 for Almost Empty flag timing and queue switching.
SKEW
is violated there will be one added RCLK cycle delay.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SKEW2
RAE
+ RCLK + t
RAE