IDT89HPES6T6G2ZCAL8 IDT, Integrated Device Technology Inc, IDT89HPES6T6G2ZCAL8 Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES6T6G2ZCAL8
• Description: IC PCI SW 6LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES6T6G2ZCAL8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES6T6G2ZCAL8

Product Description
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 6
ports across 6 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES6T6G2 can operate either as a store and forward
or cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and one Virtual Channel
IDT 89HPES6T6G2 Data Sheet
Utilizing standard PCI Express interconnect, the PES6T6G2
The PES6T6G2 is based on a flexible and efficient layered architec-
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– Supports PCI Express Device Serial Number Capability
– Capability to monitor link reliability and autonomously change
– Utilizes advanced low-power design techniques to achieve low
– Support PCI Power Management Interface specification (PCI-
– Support for PCI Express Active State Power Management
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
– Unused SerDes are disabled
– Per port link up and activity status outputs available on I/O
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
– Numerous SerDes test modes, including a PRBS Master
– Ability to read and write any internal register via SMBus and
– Per port statistics and performance counters, as well as propri-
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Power Management
Testability and Debug Features
Seven General Purpose Input/Output Pins
Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with
1mm ball spacing
• Supports device power management states: D0, D3
• Supports link power management states: L0, L0s, L1, L2/L3
• Supports optional PCI-Express SerDes Transmit Low-Swing
• Supports numerous SerDes Transmit Voltage Margin
link speed to prevent link instability
typical power consumption
PM 2.0)
(ASPM) link state
expander outputs
(PRBS) generators
Loopback mode for in-system link testing
JTAG interfaces, including SerDes internal controls
etary link status registers
D3
Ready and L3
Voltage Mode
settings
cold
hot
and
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(VC) with sophisticated resource management to enable efficient
switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
SMBus Interface
provides full access to the configuration registers in the PES6T6G2,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES6T6G2 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
consist of an SMBus clock pin and an SMBus data pin.The Master
SMBus address is hardwired to 0x50, and the slave SMBus address is
hardwired to 0x77.
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES6T6G2 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES6T6G2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES6T6G2 may be configured to operate in a split configuration as
shown in Figure 3(b).
two independent buses and thus multi-master arbitration is never
required. The PES6T6G2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
The PES6T6G2 contains two SMBus interfaces. The slave interface
Two pins make up each of the two SMBus interfaces. These pins
As shown in Figure 3, the master and slave SMBuses may be used
In the split configuration, the master and slave SMBuses operate as
PCI Express
x1
Slots
Figure 2 I/O Expansion Application
Processor
PES6T6G2
x1
x1
4xGbE
I/O
x1
Bridge
North
Processor
4xGbE
I/O
x1
SATA
September 13, 2010
I/O
Memory
Memory
Memory
x1
Memory
SATA
I/O