LTC4213IDDB#TRMPBF Linear Technology, LTC4213IDDB#TRMPBF Datasheet - Page 17

IC CIRC BREAK ELEC 8-DFN

LTC4213IDDB#TRMPBF

Manufacturer Part Number
LTC4213IDDB#TRMPBF
Description
IC CIRC BREAK ELEC 8-DFN
Manufacturer
Linear Technology
Datasheet

Specifications of LTC4213IDDB#TRMPBF

Applications
*
Mounting Type
Surface Mount
Package / Case
8-DFN
Linear Misc Type
Positive Low Voltage
Package Type
DFN EP
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
6V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Length (mm)
3mm
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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APPLICATIO S I FOR ATIO
point 6 should be within the circuit breaker limits. Other-
wise, the system fails to start and the circuit breaker trips
immediately after arming. In most applications additional
external gate capacitance is not required unless C
large and startup becomes problematic. If an external gate
capacitor is employed, its capacitance value should not be
excessive unless it is used with a series resistor. This is
because a big gate capacitor without resistor slows down
the GATE turn off during a fault. An alternative method
would be a stepped I
during startup.
In the event of output short circuit or a severe overload, the
load supply can collapse during GATE ramp up due to load
supply current limit. The chosen MOSFET must withstand
this possible brief short circuit condition before time
point 6 where the circuit breaker is allowed to trip. Bench
short circuit evaluation is a practical verification of a
reliable design. To have current limit while powering a
MOSFET into short circuit conditions, it is preferred that
the load supply sequences to turn on after the circuit
breaker is armed as described in an earlier section.
Power-Off Cycle
The system can be powered off by toggling the ON pin low.
When ON is brought below 0.76V for 5µs, the GATE and
READY pins are pulled low. The system resets when ON is
brought below 0.4V for 80µs.
MOSFET Selection
The LTC4213 is designed to be used with logic (5V) and
sub-logic (3V) MOSFETs for V
with ∆V
between 2.3V and 2.97V, sub-logic MOSFETs should be
used as the minimum ∆V
GSMAX
exceeding 4.5V. For a V
U
SEL
pin to allow a higher current limit
GSMAX
U
CC
is less than 4.5V.
potentials above 2.97V
W
CC
supply range
U
LOAD
is
The selected MOSFET V
meet the LTC4213 maximum ∆V
Other MOSFET criteria such as V
should be reviewed. Spikes and ringing above maximum
operating voltage should be considered when choosing
V
maximum operating load current is determined by the
R
Limit” for details.
Supply Requirements
The LTC4213 can be powered from a single supply or dual
supply system. The load supply is connected to the
SENSEP pin and the drain of the external MOSFET. In the
single supply case, the V
supply, preferably with an RC filter. With dual supplies,
V
V
voltage. The load supply voltage must be capable of
sourcing more current than the circuit breaker limit. If the
load supply current limit is below the circuit breaker trip
current, the LTC4213 may not react when the output
overloads. Furthermore, output overloads may trigger
UVLO if the load supply has foldback current limit in a
single supply system.
V
Input transient spikes are commonly observed whenever
the LTC4213 responds to overload. These spikes can be
large in amplitude, especially given that large decoupling
capacitors are absent in hot swap environments. These
short spikes can be clipped with a transient suppressor of
adequate voltage and power rating. In addition, the LTC4213
can detect a prolonged overvoltage condition. When
BDSS
CC
AUX
IN
DSON
Transient and Overvoltage Protection
is connected to an auxiliary bias supply V
voltage should be greater or equal to the load supply
. I
value. See the section on “Calculating Current
DMAX
should be greater than the current limit. The
GS
absolute maximum rating should
CC
pin is connected to the load
GSMAX
BDSS
, I
LTC4213
DMAX
of 8V.
, and R
AUX
17
where
DSON
4213f

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