HCS200/SN Microchip Technology, HCS200/SN Datasheet - Page 6

• Manufacturer Part Number: HCS200/SN
• Description: IC CODE HOPP ENCODER 7FUNC 8SOIC
• Manufacturer: Microchip Technology
• Type: Code Hopping Encoderr

Specifications of HCS200/SN

• Applications: Remote Secure Access, Keyless Entry
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Ic Function: Encoder IC
• Supply Voltage Range: 3.5V To 13V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 13V
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HCS200
3.0
The HCS200 contains 192 bits (12 x 16-bit words) of
EEPROM memory (Table 3-1). This EEPROM array is
used to store the crypt key information, synchronization
value, etc. Further descriptions of the memory array is
given in the following sections.
TABLE 3-1:
3.1
The 64-bit crypt key is used to create the encrypted
message transmitted to the receiver. This key is calcu-
lated and programmed during production using a key
generation algorithm. The key generation algorithm
may be different from the K
the key generation algorithm are typically the transmit-
ter’s serial number and the 64-bit manufacturer’s code.
While the key generation algorithm supplied from
Microchip is the typical method used, a user may elect
to create their own method of key generation. This may
be done providing that the decoder is programmed with
the
decryption purposes.
3.2
This is the 16-bit synchronization value that is used to
create the hopping code for transmission. This value
will increment after every transmission.
3.3
Must be initialized to 0000H.
DS40138C-page 6
ADDRESS
WORD
10
same
11
0
1
2
3
4
5
6
7
8
9
EEPROM MEMORY
ORGANIZATION
Key_0 - Key_3 (64-Bit Crypt Key)
SYNC (Synchronization Counter)
Reserved
means
KEY_0
KEY_1
KEY_2
KEY_3
SYNC
Reserved
SER_0
SER_1
SEED_0
SEED_1
Reserved
CONFIG
MNEMONIC
EEPROM MEMORY MAP
of
EE
creating
64-bit crypt key
(word 0) LSb’s
64-bit crypt key
(word 1)
64-bit crypt key
(word 2)
64-bit crypt key
(word 3) MSb’s
16-bit synchronization
value
Set to 0000H
Device Serial Number
(word 0) LSb’s
Device Serial Number
(word 1) MSb’s
Seed Value (word 0)
Seed Value (word 1)
Set to 0000H
Configuration Word
L
OQ
DESCRIPTION
algorithm. Inputs to
the
key
for
3.4
SER_0 and SER_1 are the lower and upper words of
the device serial number, respectively. Although there
are 32 bits allocated for the serial number, only the
lower order 28 bits are transmitted. The serial number
is meant to be unique for every transmitter.
3.5
The 2-word (32-bit) seed code will be transmitted when
all three buttons are pressed at the same time (see
Figure 4-2). This allows the system designer to imple-
ment the secure learn feature or use this fixed code
word as part of a different key generation/tracking pro-
cess.
3.6
The 16-bit Configuration Word stored in the EEPROM
array contains information required to form the
encrypted portion of the transmission, as well as the
device option configurations. The following sections
further explain these bits.
TABLE 3-2:
3.6.1
The discrimination value aids the post-decryption
check on the decoder end. It may be any value, but in
a typical system it will be programmed as the 12 Least
Significant bits of the serial number. Values other than
this must be separately stored by the receiver when a
transmitter is learned. The discrimination bits are part
of the information that form the encrypted portion of
the transmission (Figure 4-2). After the receiver has
decrypted a transmission, the discrimination bits are
Bit Number
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
SER_0, SER_1
(Encoder Serial Number)
SEED_0, SEED_1 (Seed Word)
Configuration Word
DISCRIMINATION VALUE
(DISC0 TO DISC11)
Reserved, set to 0
Reserved, set to 0
Discrimination Bit 0
Discrimination Bit 1
Discrimination Bit 2
Discrimination Bit 3
Discrimination Bit 4
Discrimination Bit 5
Discrimination Bit 6
Discrimination Bit 7
Discrimination Bit 8
Discrimination Bit 9
Discrimination Bit 10
Discrimination Bit 11
Low Voltage Trip Point Select (V
SEL
Baudrate Select Bit 0 (BSL0)
)
CONFIGURATION WORD
2002 Microchip Technology Inc.
Bit Description
LOW