SC414MLTRT Semtech, SC414MLTRT Datasheet - Page 26

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SC414MLTRT

Manufacturer Part Number
SC414MLTRT
Description
IC BUCK SYNC ADJ 6A 28MLPQ
Manufacturer
Semtech
Series
SmartDrive™r
Type
Step-Down (Buck)r
Datasheet

Specifications of SC414MLTRT

Mfg Application Notes
SC414 Basic Design Procedure
Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
0.75 ~ 5.5 V
Current - Output
6A
Frequency - Switching
200kHz ~ 1MHz
Voltage - Input
3 ~ 28 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-MLPQ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Other names
SC414MLTR

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Applications Information (continued)
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
tor. For a conventional PWM constant-frequency con-
verter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from V
tially constant for a given V
off set the losses the off -time will tend to reduce slightly as
load increases. The net eff ect is that switching frequency
increases slightly with increasing load.
PCB Layout Guidelines
The optimum layout for the SC414/SC424 is shown in
Figure 15. This layout shows an integrated FET buck regu-
VOUT Plane
on Top layer
PGND
shown Top Side
All components
IN
as losses increase). The on-time is essen-
AGND plane on
inner layer
OUT
and V
C
IN
OUT
combination, to
RFB1
CFF
Figure 15 — PCB Layout
RFB2
C
RES_GND — AGND connects
to PGND close to SC414/SC424
IN
L
lator with a maximum current of 6A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling Capacitors
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
Capacitors and Current Loops
A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
2 (V5V) and 3 (AGND).
RILIM
Note: This figure is not
Pin 1 marking
SC414/SC424 with
vias for LX, AGND,
to scale
LX plane on inner
V
or bottom layer
PGND on inner
IN
or bottom layer
or bottom layer
plane on inner
VIN
SC414/SC424
26

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