MAX8760ETL+T Maxim Integrated Products, MAX8760ETL+T Datasheet - Page 20

• Manufacturer Part Number: MAX8760ETL+T
• Description: IC CNTRLR QUICK PWM 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8760ETL+T

• Applications: Controller, 6-bit VID AMD Mobile Turion™
• Voltage - Input: 4 ~ 28 V
• Number Of Outputs: 2
• Voltage - Output: 0.38 ~ 1.55 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage: 0.375 V to 1.55 V
• Output Current: 4000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 550 KHz
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Buck
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TON and S0, S1 are four-level logic inputs. These inputs
help expand the functionality of the controller without
adding an excessive number of pins. The four-level
inputs are intended to be static inputs. When left open,
an internal resistive voltage-divider sets the input volt-
age to approximately 3.5V. Therefore, connect the four-
level logic inputs directly to V
selecting one of the other logic levels. See the Electrical
Characteristics table for exact logic level voltages.
When the processor enters low-power suspend mode, it
sets the regulator to a lower output voltage to reduce
power consumption. The MAX8760 includes independent
suspend-mode output voltage codes set by the four-level
S0, S1 inputs and the tri-level SUS input. When the CPU
suspends operation (SUS = REF or high), the controller
disables the offset amplifier and overrides the 5-bit VID
DAC code set by either D0–D5 (normal operation). The
master controller slews the output to the selected sus-
pend-mode voltage. During the transition, the MAX8760
blanks VROK and the UVP fault protection until 24 R
clock cycles after the slew-rate controller reaches the
suspend-mode voltage.
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
Table 3. Operating Mode Truth Table
20
SHDN
GND
V
V
V
V
V
______________________________________________________________________________________
CC
CC
CC
CC
CC
GND
GND
SUS
High
REF
or
x
x
x
Four-Level Logic Inputs
SKIP
GND
V
REF
or
CC
x
x
x
x
CC
, REF, or GND when
GND or REF
GND or REF
1.2V to 2V
Suspend Mode
0 to 0.8V
OFS
or
x
x
x
(plus offset)
SUS, S0–S1
VOLTAGE
(no offset)
(no offset)
(no offset)
OUTPUT
TIME
D0–D5
D0–D5
D0–D5
GND
GND
SUS is a tri-level logic input: GND, REF, or high. This
expands the functionality of the controller without
adding an additional pin. This input is intended to be
driven by a dedicated open-drain output with the pullup
resistor connected either to REF (or a resistive divider
from V
greater). When pulled up to REF, the MAX8760 selects
the upper suspend voltage range. When pulled high
(2.7V or greater), the controller selects the lower sus-
pend voltage range. See the Electrical Characteristics
table for exact logic-level voltages.
The MAX8760 is designed to perform mode transitions in
a controlled manner, automatically minimizing input surge
currents. This feature allows the circuit designer to
achieve nearly ideal transitions, guaranteeing just-in-time
arrival at the new output voltage level with the lowest pos-
sible peak currents for a given output capacitance.
At the beginning of an output voltage transition, the
MAX8760 blanks the VROK output, preventing it from
changing states. VROK remains blanked during the
transition and is enabled 24 clock cycles after the
slew-rate controller has set the final DAC code value.
The slew-rate clock frequency (set by resistor R
must be set fast enough to ensure that the transition is
completed within the maximum allotted time.
Low-Power Shutdown Mode. DL_ is forced high, DH_ is
forced low, and the PWM controller is disabled. The supply
current drops to 1µA (typ).
N or m al Op er ati on. The no- l oad outp ut vol tag e i s d eter m i ned b y
the sel ected V ID D AC cod e ( D 0–D 5, Tab l e 4) .
Pulse-Skipping Operation. When SKIP is pulled low, the
MAX8760 immediately enters pulse-skipping operation
allowing automatic PWM/PFM switchover under light loads.
The VROK upper threshold is blanked.
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (D0–D5, Table 4) plus the
offset voltage set by OFS.
Suspend Mode. The no-load output voltage is determined by
the selected suspend code (SUS, S0, S1, Table 5),
overriding all other active modes of operation.
Fault Mode. The fault latch has been set by either UVP, OVP,
or thermal shutdown. The controller remains in FAULT mode
until V
CC
CC
) or to a logic-level bias supply (3.3V or
power is cycled or SHDN toggled.
Output Voltage Transition Timing
OPERATING MODE
TIME
)