ISL6424ERZ Intersil, ISL6424ERZ Datasheet - Page 9

• Manufacturer Part Number: ISL6424ERZ
• Description: IC REG DUAL LNBP TTL-INP 32-QFN
• Manufacturer: Intersil

Specifications of ISL6424ERZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

in the standard-mode or up to 400Kbps in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated value
of V
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
START and STOP Conditions
As shown in Figure 3, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 4).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
SDA
SCL
SDA
SCL
DD
CONDITION
START
as per electrical specification table. One clock pulse is
S
FIGURE 3. START AND STOP WAVEFORMS
DATA VALID
DATA LINE
STABLE
FIGURE 2. DATA VALIDITY
ALLOWED
CHANGE
OF DATA
9
CONDITION
STOP
P
ISL6424
START
SDA
SCL
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6424 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6424 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
S 0 0 0 1 0 0 0 R/W ACK
read (1) or write (0) transmission) (the assigned I
address for the ISL6424 is 0001 00XX)
FIGURE 4. ACKNOWLEDGE ON THE I
MSB
TABLE 2. INTERFACE PROTOCOL
1
2
Data (8 bits)
8
2
C BUS
September 13, 2005
ACKNOWLEDGE
FROM SLAVE
2
C slave
ACK P
9
FN9175.3