LTC3735EG Linear Technology, LTC3735EG Datasheet - Page 16

IC CTRLR DC/DC 2PH HI EFF 36SSOP

LTC3735EG

Manufacturer Part Number
LTC3735EG
Description
IC CTRLR DC/DC 2PH HI EFF 36SSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC3735EG

Applications
Controller, Intel Mobile CPU
Number Of Outputs
1
Voltage - Output
0.7 ~ 1.71 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Input
-

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APPLICATIO S I FOR ATIO
LTC3735
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the
reduction of the input ripple current in a 2-phase system.
The required amount of input capacitance is further
reduced by the factor, 2, due to the reduction in input RMS
current.
The selection of C
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
output ripple (ΔV
Where f = operating frequency of each stage, C
output capacitance and ΔI
ripple currents.
ΔI
of each stage. A closed form equation can be found in
Linear Technology Application Note 77. Assuming induc-
tors are selected to have same ripple percentage for both
1-phase and 2-phase configurations, Figure 5 shows the
reduction of output ripple current by 2-phase operation.
Not only the ripple amplitude is more than halved, but the
ripple frequency is also doubled. Compared with the
output voltage ripple for 1-phase:
ΔV
given the same output capacitor ESRs. Or, to have same
ΔV
capacitors that are needed in 1-phase.
16
RIPPLE
OUT
OUT
Δ
Δ
V
V
OUT
OUT
of 2-phase is less than 50% of that of 1-phase,
2-phase only need half the number of output
can be calculated from the duty factor and the ΔI
≈ Δ
Δ
RIPPLE(P-P)
I
I
RIPPLE
RIPPLE
OUT
OUT
U
) is determined by:
is driven by the required effective
ESR
ESR
requirements. The steady state
U
RIPPLE
+
+
16 • •
8 • •
f C
= interleaved inductor
f C
1
W
1
OUT
OUT
U
OUT
=
L
The output ripple varies with input voltage since ΔI
function of input voltage. The output ripple will be less than
±25mV at max V
The LTC3735 employs OPTI-LOOP technique to compen-
sate the switching regulator loop with external compo-
nents (through I
up regulator’s transient response, minimizes output
capacitance and effectively removes constraints on out-
put capacitor ESR. It opens a much wider selection of
output capacitor types and a variety of capacitor manufac-
tures are available for high current, low voltage switching
regulators.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo has the lowest
(ESR)(size) product of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON type capacitors is recommended
to reduce the inductance effects.
C
C
OUT
OUT
required ESR < 4(R
> 1/(16f)(R
Figure 5. Output Ripple Current Reduction
of 2-Phase Over Single Phase
50
40
20
30
10
0
0.1
TH
0.2
IN
pin). OPTI-LOOP compensation speeds
SENSE
with ΔI
0.3
DUTY FACTOR (V
0.4
)
L
0.5
SENSE
= 0.4I
OUT
0.6
) and
/V
OUT(MAX)
IN
0.7
)
0.8
3735 F05
0.9
/2 assuming:
L
is a
3735f

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