ISL6564CR Intersil, ISL6564CR Datasheet - Page 16

• Manufacturer Part Number: ISL6564CR
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6564CR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
16
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.8625V
0.8500V
0.8375V
0.8250V
0.8125V
0.8000V
0.7875V
0.7750V
0.7625V
0.7500V
0.7375V
0.7250V
0.7125V
0.7000V
0.6875V
0.6750V
0.6625V
0.6500V
0.6375V
0.6250V
0.6125V
0.6000V
0.5875V
0.5750V
0.5625V
0.5500V
0.5375V
0.525V
VDAC
ISL6564
As shown in Figure 8, a current proportional to the average
current in all active channels, I
load-line regulation resistor, R
across R
creating an output voltage droop with a steady-state value
defined as
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
Where V
programmed offset voltage, I
of the converter, R
and R
r
Output-Voltage Offset Programming
The ISL6564 allows the designer to accurately adjust the
offset voltage. When a resistor, R
OFS to VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I
R
regulated to 0.5V, and I
between DAC and REF, R
product (I
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6564CR. The current flow through R
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R
For Positive Offset (connect R
For Negative Offset (connect R
V
V
R
R
DS(ON)
DROOP
OFS
DROOP
OUT
OFS
OFS
FB
is connected to ground, the voltage across it is
=
=
=
, or R
. The output voltage as a function of load current is
REF
FB
V
--------------------------
V
0.5
----------------------------- -
is the feedback resistor. R
2
OFS
V
=
REF
OFFSET
×
OFFSET
I
is proportional to the output current, effectively
×
R
AVG
is the reference voltage, V
SENSE
R
REF
x R
–
REF
V
R
OFFSET
OFS
ISEN
FB
depending on the sensing method.
) is equal to the desired offset voltage.
OFS
is the sense resistor in the ISEN line,
–
REF



flows out of OFS. A resistor
I
------------ -
OUT
OUT
FB
, is selected so that the
4
OFS
AVG
OFS
OFS
. The resulting voltage drop
OFS
is the total output current
----------------- - R
R
, flows from FB through a
OFS
to VCC):
ISEN
X
R
) to flow into OFS. If
to GND):
X
, is connected between
has a value of DCR,
:
OFS
FB
REF



is the
December 27, 2004
creates an
(EQ. 10)
(EQ. 11)
(EQ. 8)
(EQ. 9)
FN9156.2