LTC1873EG#TR Linear Technology, LTC1873EG#TR Datasheet - Page 28

• Manufacturer Part Number: LTC1873EG#TR
• Description: IC REG SW 2PH DUAL SYNC 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1873EG#TR

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 750kHz
• Duty Cycle: 93%
• Voltage - Supply: 3 V ~ 7 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Frequency-max: 750kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1873
Selection section describes in detail how to design an
optimized feedback loop, appropriate for most LTC1873
systems.
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
28
V
V
V
I
OUT
OUT
ESR
CAP
I
L
U
U
Figure 15a. Capacitor Parasitics Affecting Transient Recovery
W
TRANSIENT
HITS
Figure 15b. Transient Recovery Curves
V
SW
AROUND
TURNS
V
OUT
U
C
I
L
OUT
L
I
L
–
+
> I
+
–
V
V
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
which will cause the output voltage to fall. Since the output
voltage is initially at a high value, it can fall further before
it goes out of spec. Similarly, at full load, the output current
can only decrease, causing a positive shift in the output
voltage; the initial low value allows it to rise further before
the spec is exceeded. The primary benefit of voltage
positioning is it increases the allowable ESR of the output
capacitors, saving cost. An additional bonus is that at
maximum load, the output voltage is near the minimum
allowable, decreasing the power dissipated in the load.
OUT
ESR
CAP
1873 F15a
I
OUT
TIME
V
OUT
V
OUT(NOMINAL)
V
V
V
I
OUT
OUT
ESR
CAP
I
L
1873 F15b