LM5021NA-1/NOPB National Semiconductor, LM5021NA-1/NOPB Datasheet - Page 8

• Manufacturer Part Number: LM5021NA-1/NOPB
• Description: IC CTLR PWM AC-DC 8-MDIP
• Manufacturer: National Semiconductor

Specifications of LM5021NA-1/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 8 V ~ 30 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM5021NA-1; *LM5021NA-1/NOPB; *LM5021NA-1NOPB; LM5021NA-1; LM5021NA-1NOPB; LM5021NA-1NOPB

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RELATIONSHIP BETWEEN INPUT CAPACITOR C
V
The internal VCC linear regulator is enabled when VIN reach-
es 20V. The drop in VIN due to charge transfer from C
C
following equations where VIN' is the voltage on C
diately after the VCC regulator charges C
Assuming C
in VIN will be 0.85V, or the VIN value drops to 19.15V. The
value of the VCC capacitor can be small (less than 1uF) as it
supplies only transient gate drive current of a short duration.
The C
current and the quiescent current of LM5021until the trans-
former bias winding delivers sufficient voltage to VIN to sus-
tain the VCC voltage.
The C
VCC load current after it's output voltage reaches the VCC
UVLO threshold. For example, if the LM5021 is driving an ex-
ternal MOSFET with total gate charge (Qg) of 25nC, the
average gate drive current is Qg x Fsw, where Fsw is the
switching frequency. Assuming a switching frequency of
150KHz, the average gate drive current is 3.75mA. Since the
IC consumes approximately 2.5mA operating current in ad-
dition to the gate current, the total current drawn from C
capacitor is the operating current plus the gate charge cur-
rent, or 6.25mA. The C
for a brief time until the transformer bias winding takes over.
The C
sequence or the cycle will be restarted. The maximum allow-
able start-up time can be calculated using the value of C
the change in voltage allow at VIN (19.15V – 8.5V) and the
VCC regulator current (6.25mA). Tmax, the maximum time
allowed to energize the bias winding is:
If the calculated value of Tmax is too small, the value of Cin
should be increased further to allow more time before the
transformer bias winding takes over and delivers the operat-
ing current to the VCC regulator. Increasing C
the time from the application of the rectified ac (HV in the
Figure
old. The initial charging time of C
CC
VCC
CAPACITOR C
after the regulator is enabled can be calculated from the
VIN
VIN
VIN
2) to the time when VIN reaches the 20V start thresh-
capacitor value can be calculated from the operating
voltage must not fall below 8.5V during the start-up
capacitor must be sized to supply the gate drive
VIN
value as 10 µF, and C
(20V – V
ΔVIN x C
VCC
VIN
IN'
VIN
) C
capacitor must supply this current
= ΔVCC x C
VIN
= 8.5V C
VIN
VCC
is:
of 1µF, then the drop
VCC
VCC
VCC
.
VIN
will increase
VIN
IN
imme-
&
VIN
VIN
VIN
to
,
8
PWM COMPARATOR/SLOPE COMPENSATION
The PWM comparator compares the current sense signal with
the loop error voltage from the COMP pin. The COMP pin
voltage is reduced by 1.25V then attenuated by a 3:1 resistor
divider. The PWM comparator input offset voltage is designed
such that less than 1.25V at the COMP pin will result in a zero
duty cycle at the controller output.
For duty cycles greater than 50 percent, current mode control
circuits are subject to sub-harmonic oscillation. By adding an
additional fixed slope voltage ramp signal (slope compensa-
tion) to the current sense signal, this oscillation can be avoid-
ed. The LM5021-1 integrates this slope compensation by
summing a ramp signal generated by the oscillator with the
current sense signal. The slope compensation is generated
by a current ramp driven through an internal 1.8 kΩ resistor
connected to the CS pin. Additional slope compensation may
be added by increasing the resistance between the current
sense filter capacitor and the CS pin, thereby increasing the
voltage ramp created by the oscillator current ramp. Since the
LM5021-2 is not capable of duty cycles greater than 50%,
there is no slope compensation feature in this device.
CURRENT LIMIT/CURRENT SENSE
The LM5021 provides a cycle-by-cycle over current protec-
tion feature. Current limit is triggered by an internal current
sense comparator threshold which is set at 500mV. If the CS
pin voltage plus the slope compensation voltage exceeds
500mV, the OUT pin output pulse will be immediately termi-
nated.
An RC filter, located near the LM5021, is recommended for
the CS pin to attenuate the noise coupled from the power
FET's gate to source. The CS pin capacitance is discharged
at the end of each PWM clock cycle by an internal switch. The
discharge switch remains on for an additional 90ns leading
edge blanking interval to attenuate the current sense transient
that occurs when the external power FET is turned on. In ad-
dition to providing leading edge blanking, this circuit also
improves dynamic performance by discharging the current
sense filter capacitor at the conclusion of every cycle.
The LM5021 CS comparator is very fast, and may respond to
short duration noise pulses. Layout considerations are critical
for the current sense filter and sense resistor. The capacitor
associated with the CS filter must be placed very close to the
device and connected directly to the pins of the IC (CS and
GND). If a current sense transformer is used, both leads of
the transformer secondary should be routed to the sense re-
sistor, which should also be located close to the IC. If a current
sense resistor located in the power FET's source is used for
current sense, a low inductance resistor is required. In this
case, all of the noise sensitive low current grounds should be
connected in common near the IC and then a single connec-
tion should be made to the power ground (sense resistor
ground point).
OSCILLATOR, SHUTDOWN and SYNC CAPABILITY
A single external resistor connected between RT and GND
pins sets the LM5021 oscillator frequency. The LM5021-2 de-
vice, with 50% maximum duty cycle, includes an internal flip-
flop that divides the oscillator frequency by two. This method
produces a precise 50% maximum duty cycle limit. Because
of this frequency divider, the oscillator frequency of the
LM5021-2 is actually twice the frequency of the gate drive
output (OUT). For the LM5021-1 device, the oscillator fre-
quency and the operational output frequency are the same.
To set a desired output switching frequency (Fsw), the RT
resistor can be calculated from: