AD654JNZ Analog Devices Inc, AD654JNZ Datasheet - Page 6

• Manufacturer Part Number: AD654JNZ
• Description: IC V-F CONVERTER MONO 8-DIP
• Manufacturer: Analog Devices Inc
• Type: Voltage to Frequencyr

Specifications of AD654JNZ

• Frequency - Max: 500kHz
• Full Scale: ±50ppm/°C
• Linearity: ±0.2%
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Frequency: 500kHz
• Full Scale Range: 0kHz To 500kHz
• Linearity %: 0.03%
• Supply Voltage Range: ± 6V To ± 18V
• Digital Ic Case Style: DIP
• No. Of Pins: 8
• Input Voltage Primary Min: -14V
• Converter Function: VFC
• Full Scale Frequency: 500
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (typ): 5/9/12/15/18/24/28V
• Single Supply Voltage (max): 36V
• Single Supply Voltage (min): 4.5V
• Dual Supply Voltage (typ): ±9/±12/±15V
• Dual Supply Voltage (min): ±5V
• Dual Supply Voltage (max): ±18V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: PDIP
• Calibration Error Fs Typ: 10%
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD654
and insure the supply, source and load are appropriate. If provision
is made to trim offset, begin by setting the input to 1/10,000 of
full scale. Adjust the offset pot until the output is 1/10,000 of
full scale (for example, 25 Hz for a FS of 250 kHz). This is most
easily accomplished using a frequency meter connected to the
output. The FS input should then be applied and the gain pot
should be adjusted until the desired FS frequency is indicated.
INPUT PROTECTION
The AD654 was designed to be used with a minimum of additional
hardware. However, the successful application of a precision IC
involves a good understanding of possible pitfalls and the use of
suitable precautions. Thus +V
more than 300 mV below –V
not drop more than 500 mV below –V
nal junctions to conduct, possibly damaging the IC. In addition
to the diode shown in Figures 1 and 2 protecting Logic Common,
a second Schottky diode (MBD101) can protect the AD654’s
inputs from “below –V
desirable not to drive +V
converter will exhibit a zero output for inputs above (+V
Also, control currents above 2 mA will increase nonlinearity.
The AD654’s 80 dB dynamic range guarantees operation from a
control current of 1 mA (nominal FS) down to 100 nA (equiva-
lent to 1 mV to 10 V FS). Below 100 nA improper operation of
the oscillator may result, causing a false indication of input
amplitude. In many cases this might be due to short-lived noise
spikes which become added to input. For example, when scaled
to accept an FS input of 1 V, the –80 dB level is only 100 V, so
when the mean input is only 60 dB below FS (1 mV), noise spikes
of 0.9 mV are sufficient to cause momentary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter or a guard ring around the R
filter can be assembled using the bias current compensation
resistor discussed in the previous section. For an FS of 10 kHz,
a single-pole filter with a time constant of 100 ms will be suitable,
but the optimum configuration will depend on the application
and the type of signal processing. Noise spikes are only likely to
be a cause of error when the input current remains near its mini-
mum value for long periods of time; above 100 nA full integration
of additive input noise occurs. Like the inputs, the capacitor
terminals are sensitive to interference from other signals. The
timing capacitor should be located as close as possible to the
AD654 to minimize signal pickup in the leads. In some cases,
guard rings or shielding may be required.
DECOUPLING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 to
100 ) in the supply lines to provide a measure of decoupling
Figure 5. Input Protection
I
IN
S
’’ inputs as shown in Figure 5. It is also
IN
and R
MBD101
IN
S
. Likewise, Logic Common should
and R
T
AD654
above +V
T
S
pins should not be driven
. This would cause inter-
S
. In operation, the
T
pin. The
S
– 3.5 V).
–6–
between the various circuits in the system. Ceramic capacitors
of 0.1 F to 1.0 F should be applied between the supply-
voltage pins and analog signal ground for proper bypassing on
the AD654. A proper ground scheme appears in Figure 6.
OUTPUT INTERFACING CONSIDERATION
The output stage’s design allows easy interfacing to all digital logic
families. The output NPN transistor’s emitter and collector are
both uncommitted. The emitter can be tied to any voltage between
–V
up to a voltage 36 volts above the emitter regardless of +V
high power output stage can sink over 10 mA at a maximum
saturation voltage of 0.4 V. The stage limits the output current
at 25 mA and can handle this limit indefinitely without damag-
ing the device.
NONLINEARITY SPECIFICATION
The preferred method of specifying nonlinearity error is in terms
of maximum deviation from the ideal relationship after calibrat-
ing the converter at full scale. This error will vary with the full
scale frequency and the mode of operation. The AD654 operates
best at a 150 kHz full-scale frequency with a negative voltage input;
the linearity is typically within 0.05%. Operating at higher fre-
quencies or with positive inputs will degrade the linearity as
indicated in the Specifications Table. Typical linearity at various
temperatures is shown in Figure 7.
Figure 7. Typical Nonlinearities at Different Full-Scale
Frequencies
S
AGND
and 4 volts below +V
f
OUT
V
0.10
0.05
0.01
IN
0.5
10
5
1
R
10
PU
Figure 6. Proper Ground Scheme
1
8
FULL-SCALE FREQUENCY – kHz
150
7
2
AD654
S
, and the open collector can be pulled
C
T
3
6
f
R
AMB
T
250
= 0 C TO +85 C
4
5
f
0.1 F
AMB
10
= –40 C
350
+5V
GND
DIGITAL
P.S.
500
REV. B
S
. The