LTC1966CMS8 Linear Technology, LTC1966CMS8 Datasheet - Page 22

• Manufacturer Part Number: LTC1966CMS8
• Description: IC PREC RMS/DC CONV MCRPWR 8MSOP
• Manufacturer: Linear Technology

Specifications of LTC1966CMS8

• Current - Supply: 155µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1966
Obviously, the effect of crest factor is somewhat simplified
above given the factor of two difference based on a
subjective description of the waveform type. The results
will vary somewhat based on actual crest factor and
waveform dynamics and the type of filtering used. The
above method is conservative for some cases and about
right for others.
The LTC1966 works well with signals whose crest factor
is 4 or less. At higher crest factors, the internal
modulator will saturate, and results will vary depending on
the exact frequency, shape and (to a lesser extent) ampli-
tude of the input waveform. The output voltage could be
higher or lower than the actual RMS of the input signal.
The
crest factors less than 4 are used with insufficient averag-
ing. This will only occur when the output droops to less
than 1/4 of the input voltage peak. For instance, a DC-
coupled pulse train with a crest factor of 4 has a duty cycle
of 6.25% and a 1V
50Hz, repeating every 20ms, and C
will droop during the inactive 93.75% of the waveform.
This droop is calculated as:
For the LTC1966, whose output impedance (Z
85k , this droop works out to – 5.22%, so the output
would be reduced to 237mV at the end of the inactive
portion of the input. When the input signal again climbs to
1V
With C
and the peak/output ratio is just 4.022, which the LTC1966
has enough margin to handle without error.
For crest factors less than 3.5, the selection of C
previously described should be sufficient to avoid this
droop and modulator saturation effect. But with crest
factors above 3.5, the droop should also be checked for
each design.
Error Analyses
Once the RMS-to-DC conversion circuit is working, it is
time to take a step back and do an analysis of the accuracy
22
PEAK
V
MIN
AVE
, the peak/output ratio is 4.22.
modulator may also saturate when signals with
= 10 F, the droop is only – 0.548% to 248.6mV
V
RMS
2
PEAK
1–
U
e
input is 250mV
2 • Z
INACTIVE TIME
U
OUT
• C
W
AVE
AVE
RMS
= 1 F, the output
. If this input is
U
OUT
AVE
) is
as
of that conversion. The LTC1966 specifications include
three basic static error terms, V
output offset is an error that simply adds to (or subtracts
from) the voltage at the output. The conversion gain of the
LTC1966 is nominally 1.000 V
error reflects the extent to which this conversion gain is
not perfectly unity. Both of these affect the results in a
fairly obvious way.
Input offset on the other hand, despite its conceptual
simplicity, effects the output in a nonobvious way. As its
name implies, it is a constant error voltage that adds
directly with the input. And it is the sum of the input and
V
This means that the effect of V
nonlinear RMS conversion. With 0.2mV (typ) V
200mV
and AC terms in an RMS fashion and the effect is
negligible:
But with 10 less AC input, the error caused by V
100 larger:
This phenomena, although small, is one source of the
LTC1966’s residual nonlinearity.
On the other hand, if the input is DC coupled, the input
offset voltage adds directly. With +200mV and a +0.2mV
V
1000ppm. With DC inputs, the error caused by V
positive or negative depending if the two have the same or
opposing polarity.
The total conversion error with a sine wave input using the
typical values of the LTC1966 static errors is computed as
follows:
IOS
IOS
V
V
V
OUT
OUT
OUT
, a 200.2mV output will result, an error of 0.1% or
that is RMS converted.
RMS
= (200mV AC)
= 200.0001mV
= 200mV + 1/2ppm
= (20mV AC)
= 20.001mV
= 20mV + 50ppm
= 500.600mV
= 500mV + 0.120%
= ( (500mV AC)
AC input, the RMS calculation will add the DC
2
2
+ (0.2mV DC)
2
+ (0.2mV DC)
+ (0.2mV DC)
DCOUT
OOS
IOS
, V
/V
RMSIN
2
IOS
is warped by the
2
2
) • 1.001 + 0.1mV
and GAIN. The
and the gain
IOS
IOS
sn1966 1966fas
, and a
can be
IOS
is