LM3881MMX/NOPB National Semiconductor, LM3881MMX/NOPB Datasheet - Page 7

• Manufacturer Part Number: LM3881MMX/NOPB
• Description: IC POWER SUPPLY SEQUENCER 8MSOP
• Manufacturer: National Semiconductor

Specifications of LM3881MMX/NOPB

• Applications: Power Supply Sequencer
• Voltage - Input: 2.7 ~ 5.5 V
• Current - Supply: 80µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• For Use With: LM3881EVAL - BOARD EVALUATION FOR LM3881
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: LM3881MMX

Application Information
OVERVIEW
The LM3881 Power Sequencer provides a simple solution for
sequencing multiple rails in a controlled manner. A clock sig-
nal is established that facilitates control of the power up and
power down of three open drain FET output flags. These flags
permit connection to shutdown or enable pins of linear regu-
lators and/or switching regulators to control the power sup-
plies’ operation. This allows a complete power system to be
designed without worrying about large in-rush currents or
latch-up conditions that can occur during an uncontrolled
startup. An invert (INV) pin is provided that reverses the logic
Thus, the clock cycle duration is directly proportional to the
timing capacitor value. Considering the TADJ voltage thresh-
old levels and the charge/discharge current magnitude, it can
be shown that the timing capacitor-clock period relationship
is typically 120 µs/nF. For example, a 10 nF capacitor sets up
a clock period of 1.2 ms.
The timing sequence of the LM3881 is controlled by the en-
able (EN) pin. Upon power up, all the flags are held low until
the precision enable pin exceeds its threshold. After the EN
pin is asserted, the power up sequence will commence and
the open-drain flags will be sequentially released.
An internal counter will delay the first flag (FLAG1) from rising
until a fixed time period, denoted by T
diagram, elapses. This corresponds to at least nine, maxi-
mum ten, clock cycles depending on where EN is asserted
relative to the clock signal. Upon release of the first flag, an-
D1
in the following timing
FIGURE 1. TADJ Pin Timing Waveform
7
of the output flags. This pin should be tied to a logic output
high or low and not allowed to remain open circuit. The fol-
lowing discussion assumes the INV pin is held low such that
the flag output is active high.
A small external timing capacitor is connected to the TADJ
pin that establishes the clock waveform. This capacitor is lin-
early charged/discharged by a fixed current source/sink, de-
noted I
defined voltage threshold levels, denoted V
generate the timing waveform as shown in the following dia-
gram.
other timer will begin to delay the release of the second flag
(FLAG2). This time delay, denoted T
actly eight clock periods. Similarly, FLAG3 is released after
time delay T
ingly, a TADJ capacitor of 10 nF generates typical time delays
T
ms.
The power down sequence is the same as power up, but in
reverse order. When the EN pin is de-asserted, a timer will
begin that delays the third flag (FLAG3) from pulling low. The
second and first flag will then follow in a sequential manner
after their appropriate time delays. These time delays, denot-
ed T
For robustness, the pull down FET associated with each flag
is designed such that it can sustain a short circuit to VCC.
D2
and T
D4
, T
TADJ_SRC
D5
D3
, T
D3
of 9.6 ms and T
D6
, again eight clock cycles, has expired. Accord-
/ I
, are equal to T
TADJ_SNK
, of magnitude 12 µA between pre-
D1
30048409
of between 10.8 ms and 12.0
D1
, T
D2
D2
, T
, corresponds to ex-
D3
, respectively.
LTH
and V
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, to