IR3086M International Rectifier, IR3086M Datasheet - Page 7

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IR3086M

Manufacturer Part Number
IR3086M
Description
IC PHASE CONTROLLER 20-MLPQ
Manufacturer
International Rectifier
Series
XPhase™r
Datasheet

Specifications of IR3086M

Applications
Processor
Current - Supply
10mA
Voltage - Supply
8.4 V ~ 14 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-MLPQ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*IR3086M

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PWM Control Method
The PWM block diagram of the XPhase
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes
in load current.
Frequency and Phase Timing Control
An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty
cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used
to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by
resistor divider R
comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the
resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS
voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note
that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins,
as shown in Figure 2.
+
-
Page 7 of 34
50%
DUTY
CYCLE
VBIAS
REGULATOR
CONTROL IC
RAMP GENERATOR
IFB
+
-
ERROR
AMP
IROSC
VDAC
PHS1
VPEAK
VVALLEY
+
-
VDRP
AMP
and R
VDRP
IIN
RMPOUT
VBIAS
VDAC
VOSNS-
EAOUT
FB
PHS2
connected between the VBIAS reference voltage and the Phase IC LGND pin. A
RVFB
RDRP
TM
architecture is shown in Figure 2. Feed-forward voltage mode control with
Figure 2. PWM Block Diagram
RPWMRMP
CPWMRMP
RPWMRMP
CPWMRMP
RPHS1
RPHS2
RPHS1
RPHS2
CSCOMP
CSCOMP
RAMPIN+
RAMPIN-
PWMRMP
RAMPIN+
RAMPIN-
PWMRMP
SCOMP
ISHARE
DACIN
SCOMP
ISHARE
DACIN
BIASIN
EAIN
BIASIN
EAIN
SHARE
ADJUST
ERROR
AMPLIFIER
SHARE
ADJUST
ERROR
AMPLIFIER
+
-
+
-
SYSTEM
REFERENCE
VOLTAGE
SYSTEM
REFERENCE
VOLTAGE
10K
10K
CLOCK
PULSE
GENERATOR
CLOCK
PULSE
GENERATOR
+
-
+
-
20mV
20mV
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
PWM
COMPARATOR
PWM
COMPARATOR
ENABLE
ENABLE
PHASE IC
PHASE IC
-
+
-
+
+
-
+
-
PWM
LATCH
DOMINANT
PWM
LATCH
DOMINANT
S
RESET
R
BODY
BRAKING
COMPARATOR
S
RESET
R
BODY
BRAKING
COMPARATOR
CURRENT
SENSE
AMPLIFIER
X34
CURRENT
SENSE
AMPLIFIER
X34
+
-
+
-
X
0.91
X
0.91
CSIN-
CSIN-
GATEH
GATEL
CSIN+
GATEH
GATEL
CSIN+
CCS
CCS
RCS
RCS
9/30
IR3086
/04
COUT
VIN
VOSNS+
VOUT
GND
VOSNS-

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