MIC2564A-1BSM TR Micrel Inc, MIC2564A-1BSM TR Datasheet - Page 5

• Manufacturer Part Number: MIC2564A-1BSM TR
• Description: IC PCMCIA/CARDBUS DUAL 24-SSOP
• Manufacturer: Micrel Inc
• Type: PCMCIA/Cardbus Switchr

Specifications of MIC2564A-1BSM TR

• Number Of Outputs: 4
• Rds (on): 5 Ohm
• Internal Switch(s): Yes
• Current Limit: 260mA
• Voltage - Input: 3.3V, 5V, 12V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MIC2564A-1BSMTR; MIC2564A-1BSMTR

Symbol
Thermal Shutdown
T
Serial Interface DC Specifications
V
V
I
Flag
I
Serial Interface Timing Requirements (See Figures 1 and 2)
t
t
t
t
t
t
t
Notes:
14. Guaranteed by design not production tested.
15. Guaranteed by characterization but not production tested.
Serial Control Timing Diagram
The MIC2564A uses a three-wire serial interface to control V
lines have thresholds compatible with both 3.3V and 5V logic families. Data (SDA) is clocked in on the rising clock edge. The
clock signal may be continuous or it may halt after all data is clocked in.
March 2004
MIC2564A
IN
FLG
HD:DAT
SU:DAT
SU:SLA
SU:RST#
W
R
F
SD
IH
IL
RST#
SDA
SCL
SLA
Parameter
Thermal Shutdown Temperature
Input Voltage: SDA, SCL, SLA pins
Input Voltage: SDA, SCL, SLA pins
Input Current
Flag Leakage Current
SDA Hold Time
SDA Setup Time
Latch Setup Time
Reset to Data Setup Time
Minimum Pulse Width
SCL Rise Time
SCL Fall Time
t
SU:RST#
SCL
t
SU:DAT
D8
Figure 1. Serial Control Timing Diagram
D7
t
10%
r
Figure 2. SCL Rise and Fall Times
90%
D6
t
HD:DAT
Conditions
0V < V
V
Data before clock
RST# before data
Clock (t
Latch (t
Reset (t
Data (t
f = 32kHz
f = 32kHz
FLG
t
D5
= 5V
W:DAT
IN
W:DA
W:SLA
W:CLK
W:RST
(14)
< 5.5V
(15)
(15)
)
CC
D4
5
)
)
)
t
and V
W:CLK
D3
PP
outputs for both sections A and B. The three control
90%
D2
10%
t
f
D1
t
SU:SLA
D0
0.7V
–0.3
Min
100
–1
75
75
50
50
50
50
50
0
0
CC3
IN
t
W:SLA
Typ
145
0.2
0.3V
Max
100
100
5.5
M0250-031104
1
1
CC3
IN
Micrel
Units
mA
mA
∞C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V