IRS2168DSPBF International Rectifier, IRS2168DSPBF Datasheet - Page 13

• Manufacturer Part Number: IRS2168DSPBF
• Description: IC PFC/BALLAST CONTROL 16-SOIC
• Manufacturer: International Rectifier
• Type: PFC/Ballast Controllerr

Specifications of IRS2168DSPBF

• Frequency: 42.5 ~ 46.5 kHz
• Current - Supply: 10mA
• Current - Output: 260mA
• Voltage - Supply: 12.5 V ~ 15.6 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• Package: 16-lead SOIC
• Circuit: PFC Ballast Control and Half-Bridge Driver
• Offset Voltage (v): 600
• Output Source Current Min (ma): 180
• Output Sink Current Min (ma): 260
• Pbf: Yes
• For Use With: IRPLLNR5 - KIT BALLAST UNIV FLUOR 54W TL5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ignition voltage) of the ballast output stage. Should this
voltage exceed the internal threshold of 1.2 V (V
ignition regulation circuit controls the voltage on the VCO
pin to increase the frequency slightly (see Fig. 6). This
cycle-by-cycle feedback from the C
will adjust the frequency each cycle to limit the amplitude
of the current for the entire duration of ignition mode.
When C
time, the IC enters run mode and the fault counter
becomes enabled. The ignition regulation disabled in run
mode but the IC will enter fault mode after 65 (n
consecutive over-current faults and gate driver outputs
HO, LO and PFC will be latched low.
The output voltage of the ballast will increase during the
ignition ramp t
from the preheat frequency to the ignition frequency and
will be constant during ignition because the ignition
regulation circuit will regulate the amplitude of the current
for the entire duration of the ignition time t
8).
During ignition mode, the PFC circuit is working in high-
gain mode and keeps the DC bus voltage regulated at a
constant level.
prevent the DC bus from decreasing during lamp ignition
or ignition regulation. Also during ignition mode, the
SD/EOL fault is disabled.
1.25V
V
V
HO
LO
VS
VCO
CS
2V
Figure 6: Ignition regulation timing diagram
PH
exceeds 2/3*V
RAMP
The high-gain mode is necessary to
because the frequency ramp down
CC
(V
CPHRUN+
S
pin to the VCO pin
) for the second
IGN
(Figs. 7 and
CSTH+),
EVENTS
t
t
t
the
)
preheat and ignition with deactivated lamp, time span
preheat and ignition with deactivated lamp, time span
Figure 8: Ballast output voltage and CPH pin during
Figure 7: Ballast output voltage and CPH pin during
V
V
OUT
CPH
t
RAMP
t
PH
100ms
50ms
V
V
OUT
CPH
IRS2168D(S)PbF
t
t
RAMP
IGN
t
IGN
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