PCA9511ADP,118 NXP Semiconductors, PCA9511ADP,118 Datasheet
PCA9511ADP,118
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935279308118
PCA9511ADP-T
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PCA9511ADP,118 Summary of contents
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PCA9511A Hot swappable I Rev. 04 — 19 August 2009 1. General description The PCA9511A is a hot swappable I insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected ...
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... NXP Semiconductors 3. Applications I cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. Feature selection Table 1. Feature selection chart Feature idle detect high-impedance SDA, SCL pins for V rise time accelerator circuitry on SDAn and SCLn lines ...
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... NXP Semiconductors 6. Block diagram PCA9511A SLEW RATE DETECTOR SDAIN CONNECT 100 k RCH1 100 k RCH2 SLEW RATE DETECTOR SCLIN CONNECT 0.55V / CC 0.45V CC UVLO 100 s ENABLE DELAY Fig 1. Block diagram of PCA9511A PCA9511A_4 Product data sheet Hot swappable SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning ENABLE SCLOUT SCLIN Fig 2. 7.2 Pin description Table 3. Symbol ENABLE SCLOUT SCLIN GND READY SDAIN SDAOUT Functional description Refer to 8.1 Start-up An undervoltage/initialization circuit holds the parts in a disconnected state which presents high-impedance to all SDA and SCL pins during power-up. A LOW on the ENABLE pin also forces the parts into the low current disconnected state when the I essentially zero ...
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... NXP Semiconductors is activated during the initialization and is deactivated when the connection is made. The precharge circuitry pulls up the SDA and SCL pins through individual 100 k nominal resistors. This precharges the pins minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels ...
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... NXP Semiconductors on the accelerator turns the pull-down off. If the V detected, the pull-down will turn off and will not turn back on until a falling edge is detected. Fig 4. Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of buffer A and buffer B ...
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... NXP Semiconductors turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, V well as the load current and the load capacitance. 8.5 Rise time accelerators During positive bus transitions current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0 ...
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... NXP Semiconductors (1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A. (2) Rise time without PCA9511A. Fig (1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A. (2) Rise time without PCA9511A. Fig 6. PCA9511A_4 Product data sheet max 40 30 (2) rise time = 300 ns ...
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... NXP Semiconductors 8.9 Hot swapping and capacitance buffering application Figure 7 advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements diffi ...
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... NXP Semiconductors BACKPLANE CONNECTOR BACKPLANE SDA SCL Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a PCI system ENABLE SDA1 SDAIN SCLIN SCL1 to other System 1 devices Remark: See Application Note AN255, ‘I optimized for long distance transmission of the I Fig 9 ...
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... NXP Semiconductors Fig 10. System with disparate V 9. Application design-in information Fig 11. Typical application 10. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol oper T stg j(max) [1] Voltages with respect to pin GND. PCA9511A_4 Product data sheet R drop ...
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... NXP Semiconductors 11. Characteristics Table 5. Characteristics +85 V; unless otherwise specified. CC amb Symbol Parameter Power supply V supply voltage CC I supply current CC I Shut-down mode supply CC(sd) current Start-up circuitry V precharge voltage pch V HIGH-level input voltage IH(ENABLE) on pin ENABLE V LOW-level input voltage ...
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... NXP Semiconductors Table 5. Characteristics …continued +85 V; unless otherwise specified. CC amb Symbol Parameter Input-output connection V offset voltage offset t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay C SCL and SDA input i(SCL/SDA) capacitance V LOW-level output OL voltage I input leakage current ...
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... NXP Semiconductors [9] Force 0.1 V, tie SDAOUT and SCLOUT through 10 k resistor to V SDAIN SCLIN output. 11.1 Typical performance characteristics 3 (mA) 3.3 2.9 2.5 40 +25 Fig 12. I versus temperature 5 PHL (ns) 80 2 > 100 pF PU(in) Fig 14. Input/output t versus temperature PHL PCA9511A_4 Product data sheet ...
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... NXP Semiconductors 11.2 Timing diagrams SDAn/SCLn ENABLE READY Fig 16. Timing for idle(READY) SDAIN SCLIN SCLOUT SDAOUT ENABLE READY t is only applicable after the t stp(READY) Fig 17. t that can occur after t stp(READY) SCLIN, SDAIN, SCLOUT, SDAOUT ENABLE READY t is only applicable after the t stp(READY) Fig 18 ...
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... NXP Semiconductors 12. Test information R = load resistor load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 19. Test circuitry for switching times PCA9511A_4 Product data sheet Hot swappable PULSE DUT GENERATOR Rev. 04 — 19 August 2009 PCA9511A ...
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... NXP Semiconductors 13. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 8. Acronym AdvancedTCA CDM cPCI ESD HBM 2 I C-bus MM PCI PICMG SMBus VME ...
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... NXP Semiconductors 16. Revision history Table 9. Revision history Document ID Release date PCA9511A_4 20090819 • Modifications: Section 8.8 “Resistor pull-up value “... always choose R to “... always choose R maximum.” • Figure 5 “Bus requirements for 3.3 V systems” – changed from “rise time > 300 ns” to “rise time = 300 ns” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 4 8.1 Start-up 8.2 Connect circuitry 8.3 Maximum number of devices in series . . . . . . . 5 8.4 Propagation delays . . . . . . . . . . . . . . . . . . . . . . 6 8 ...