ADE7754AR Analog Devices Inc, ADE7754AR Datasheet - Page 27

• Manufacturer Part Number: ADE7754AR
• Description: IC ENERY METER 3PHASE 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7754AR

• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD71049AR; AD71049AR

The number of half line cycles is specified in the LINCYC unsigned
16-bit register. The ADE7754 can accumulate apparent power
for up to 65535 combined half cycles. Because the apparent
power is integrated on the same integral number of line cycles as
the line active energy register, these two values can be compared
easily. See the Energies Scaling section. The active and apparent
energy are calculated more accurately because of this precise
timing control and provide all the information needed for reactive
power and power factor calculation. At the end of an energy
calibration cycle, the LINCYC flag in the interrupt status register
is set. If the LINCYC enable bit in the interrupt enable register
is set to Logic 1, the IRQ output also goes active low. Thus the
IRQ line can also be used to signal the end of a calibration.
The total apparent power calculated by the ADE7754 in the
line accumulation mode depends on the configuration of the
VAMOD bits in the VAMode register. Each term of the formula
used can be disabled or enabled by the LVASEL bits of the
VAMode register. The different configurations are described in
Table VI.
VAMOD VASEL0
0d
1d
2d
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of
these two registers is equivalent.
The ADE7754 accumulates the total reactive power signal in
the LAENERGY register. This mode is selected by setting to
Logic 1 Bit 5 of the WAVMode register (Address 0Ch). When
this bit is set, the accumulation of the active energy over half
line cycles in the LAENERGY register is disabled and done
instead in the LVAENERGY register. In this mode, the accu-
REV. 0
FROM VA
ADC
FROM VB
ADC
FROM VC
ADC
Table VI. Total Line Apparent Energy Calculation
LPF1
LPF1
LPF1
V
V
V
ARMS
ARMS
ARMS
× I
× I
× I
ZERO-CROSS
ZERO-CROSS
ZERO-CROSS
ARMS
ARMS
ARMS
DETECT
DETECT
DETECT
REGISTER BIT 4
REGISTER BIT 5
REGISTER BIT 6
VASEL1
+ V
+(V
/2 × I
+ V
MMODE
MMODE
MMODE
BRMS
ARMS
ARMS
BRMS
× I
× I
+ V
BRMS
BRMS
CRMS
)
Figure 39. Apparent Energy Calibration
VASEL2
+ V
+ V
+ V
CRMS
CRMS
CRMS
× I
× I
× I
CRMS
CRMS
CRMS
CALIBRATION
LINCYC[15:0]
ACCUMULATE APPARENT POWER
DURING LINCYC ZERO CROSSINGS
CONTROL
–27–
mulation of the apparent energy over half line cycles in the
LVAENERGY is no longer available. See Figure 33. Since the
LVAENERGY register is an unsigned value, the accumulation
of the active energy in the LVAENERGY register is unsigned.
In this mode (reactive energy), the selection of the phases
accumulated in the LAENERGY and LVAENERGY registers
is done by the LWATSEL selection bits of the WATMode
register.
ENERGIES SCALING
The ADE7754 provides measurements of the active, reactive,
and apparent energies. These measurements do not have the
same scaling and thus cannot be compared directly to each other.
Energy
Type
Active
Reactive
Apparent Wh / 3.657
CHECK SUM REGISTER
The ADE7754 has a checksum register (CHECKSUM[5:0]) to
ensure that the data bits received in the last serial read operation
are not corrupted. The 6-bit checksum register is reset before
the first bit (MSB of the register to be read) is put on the
DOUT pin. During a serial read operation, when each data bit
becomes available on the rising edge of SCLK, the bit is added
to the checksum register. In the end of the serial read operation,
the content of the checksum register will equal the sum of all
ones in the register previously read. Using the checksum regis-
ter, the user can determine whether an error has occurred during
the last read operation. Note that a read to the checksum register
also generates a checksum of the checksum register itself.
CONTENT OF REGISTER (n-BYTES)
Figure 40. Checksum Register for Serial Interface Read
APPARENT
POWER
PHASE B
APPARENT
POWER
PHASE A
APPARENT
POWER
PHASE C
PF = 1
Wh
0
+
+
+
PF = 0.707
Wh
Wh
Wh / 3.657
+
0.707
0.707 / 9.546
VADIV
+
48
LVAENERGY[23:0]
48
23
CHECKSUM
REGISTER
ADE7754
DOUT
%
PF = 0
0
Wh / 9.546
Wh / 3.657
0
ADDR: 3Eh
0
0