ADE7763ARSZRL Analog Devices Inc, ADE7763ARSZRL Datasheet - Page 48

• Manufacturer Part Number: ADE7763ARSZRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7763ARSZRL

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Ic Function: Single-Phase Active And Apparent Energy Metering IC
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
• Lead Free Status / Rohs Status: Compliant
• Other names: ADE7763ARSZRL; ADE7763ARSZRLTR

ADE7763
Address
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
APOS
WGAIN
WDIV
CFNUM
CFDEN
IRMS
VRMS
IRMSOS
VRMSOS
VAGAIN
VADIV
LINECYC
ZXTOUT
SAGCYC
SAGLVL
IPKLVL
VPKLVL
IPEAK
RSTIPEAK
VPEAK
RSTVPEAK
Name
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
12
24
24
12
16
8
8
8
24
24
24
24
No. Bits
16
12
8
12
12
12
8
12
8
Default
0x0
0x0
0x0
0x3F
0x3F
0x0
0x0
0x0
0x0
0x0
0x0
0xFFFF
0xFFF
0xFF
0x0
0xFF
0xFF
0x0
0x0
0x0
0x0
Type
S
S
U
U
U
U
U
S
S
S
U
U
U
U
U
U
U
U
U
U
U
Rev. B | Page 48 of 56
1
Description
Active Power Offset Correction. This 16-bit register allows small offsets in
the active power calculation to be removed—see the Active Power
Calculation section.
Power Gain Adjust. This is a 12-bit register. Calibrate the active power
calculation by writing to this register. The calibration range is ±50% of the
nominal full-scale active power. The resolution of the gain adjust is
0.0244%/LSB —see the Calibrating an Energy Meter section.
Active Energy Divider Register. The internal active energy register is
divided by the value of this register before being stored in the AENERGY
register.
CF Frequency Divider Numerator Register. Adjust the output frequency
on the CF pin by writing to this 12-bit read/write register—see the
Energy-to-Frequency Conversion section.
CF Frequency Divider Denominator Register. Adjust the output frequency
on the CF pin by writing to this 12-bit read/write register—see the
Energy-to-Frequency Conversion section.
Channel 1 RMS Value (Current Channel).
Channel 2 RMS Value (Voltage Channel).
Channel 1 RMS Offset Correction Register.
Channel 2 RMS Offset Correction Register.
Apparent Gain Register. Calibrate the apparent power calculation by
writing to this register. The calibration range is 50% of the nominal full-
scale real power. The resolution of the gain adjust is 0.02444%/LSB.
Apparent Energy Divider Register. The internal apparent energy register
is divided by the value of this register before being stored in the
VAENERGY register.
Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit
register is used during line cycle energy accumulation mode to set the
number of half line cycles for energy accumulation—see the Line Cycle
Energy Accumulation Mode section.
Zero-Crossing Timeout. If no zero crossings are detected on Channel 2
within the time specified in this 12-bit register, the interrupt request line
( IRQ ) will be activated—see the
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive line cycles below SAGLVL that is required on Channel 2
before the SAG output is activated—see the Line Voltage Sag Detection
section.
Sag Voltage Level. An 8-bit write to this register determines at what peak
signal level on Channel 2 the SAG pin becomes active. The signal must
remain low for the number of cycles specified in the SAGCYC register
before the SAG pin is activated—see the
section.
Channel 1 Peak Level Threshold (Current Channel). This register sets the
level of current peak detection. If the Channel 1 input exceeds this level,
the PKI flag in the status register is set.
Channel 2 Peak Level Threshold (Voltage Channel). This register sets the
level of voltage peak detection. If the Channel 2 input exceeds this level,
the PKV flag in the status register is set.
Channel 1 Peak Register. The maximum input value of the current
channel, since the last read of the register is stored in this register.
Same as Channel 1 peak register, except that the register contents are
reset to 0 after a read.
Channel 2 Peak Register. The maximum input value of the voltage
channel, since the last read of the register is stored in this register.
Same as Channel 2 peak register, except that the register contents are
reset to 0 after a read.
Zero-Crossing Detection
Line Voltage Sag Detection
section.