FSQ100 Fairchild Semiconductor, FSQ100 Datasheet - Page 8

• Manufacturer Part Number: FSQ100
• Description: IC SWIT PWM GREEN OVP HV 8DIP
• Manufacturer: Fairchild Semiconductor

Specifications of FSQ100

• Output Isolation: Isolated
• Frequency Range: 61 ~ 73kHz
• Voltage - Input: 8 ~ 20 V
• Voltage - Output: 650V
• Power (watts): 8W
• Operating Temperature: 25°C ~ 145°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Power Switch Family: FSQ100
• Power Switch On Resistance: 16Ohm
• Output Current: 475mA
• Number Of Outputs: Single
• Mounting: Through Hole
• Supply Current: 1.5mA
• Package Type: PDIP W
• Operating Temperature (min): -25C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Pin Count: 8
• Power Dissipation: 1.4W
• On Resistance (max): 16 Ohms
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Maximum Power Dissipation: 1400 mW
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2007 Fairchild Semiconductor Corporation
FSQ100 Rev. 1.0.2
Functional Description
1. Startup: At startup, the internal high-voltage current
source supplies the internal bias and charges the
external V
V
internal high-voltage current source stops charging the
capacitor. The device is in normal operation provided
V
supplied from the auxiliary transformer winding.
Calculating the V
design with the FSQ100. At initial startup, the maximum
value of start operating current I
which supplies current to UVLO and V
charging current I
– 100µA. After V
the bias winding supplies V
When the bias winding voltage is not sufficient, the V
level decreases to the UVLO stop voltage and the
internal current source is activated again to charge the
V
(charging/discharging), the V
chosen to have a value between 10µF and 47µF.
2. Feedback Control: The FSQ100 is a voltage mode
controlled device, as shown in Figure 16. Usually, an
opto-coupler and shunt regulator, like KA431 are used
to implement the feedback network. The feedback
voltage is compared with an internally generated
sawtooth waveform. This directly controls the duty cycle.
CC
CC
CC
Figure 15.
V
does not drop below 7V. After startup, the bias is
V
reaches 9V, the device starts switching and the
V
START
STOP
CC
capacitor.
Figure 14.
CC
I
Vc c
V
capacitor, as shown in Figure 14. When
I
Vcc
IN
= I
UV LO
Charging V
,dc
STR
= I
CC
V
VCC
STR
CC
IN
- I
To
STAR T
reaches the UVLO start voltage, only
,dc
-I
START
V
of the V
capacitor is an important step to
V
CC
Internal Startup Circuit
CC
prevent
CC
9V/ 7V
I
STAR T
CC
V
CC
Capacitor through Vstr
CC
Bias winding
CC
below V
U VLO
capacitor is equal to I
voltage
V
must not drop
I
current to the device.
STR
ref
START
this
capacitor should be
L
STOP
H
V
J-FET
STR
is about 100µA,
V
I
REF
STR
Vstr
CC
blocks. The
fluctuation
t
STR
CC
8
When the shunt regulator reference pin voltage exceeds
the internal reference voltage of 2.5V, the opto-coupler
LED current increases, the feedback voltage V
pulled down, and it reduces the duty cycle. This
happens when the input voltage increases or the output
load decreases.
3. Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, the primary-side
capacitance and secondary-side rectifier diode reverse
recovery typically causes a high-current spike through
the SenseFET. Excessive voltage across the R
resistor lead to incorrect pulse-by-pulse current limit
protection. To avoid this, a leading edge blanking (LEB)
circuit disables pulse-by-pulse current-limit protection
block for a fixed time (t
4. Protection Circuit: The FSQ100 has protective
functions, such as overload protection (OLP), over
voltage protection (OVP), under-voltage lockout (UVLO),
and thermal shutdown (TSD). Because these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
costs. Once a fault condition occurs, switching is
terminated and the SenseFET remains off. This causes
V
V
voltage current source charges the V
V
V
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated.
CC
STOP
STR
START
to fall. When V
pin. When V
(7V), the protection is reset and the internal high-
V O
Figure 16.
(9V), the device resumes normal operation. In
V
C
fb
fb
KA431
4
Figure 17.
5 µA
RESET
V fb
C
CC
fb
CC
PWM and Feedback Circuit
4
5µA
V
400µA
+
fb
V
reaches the UVLO start voltage
V
LEB
CC
SD
reaches the UVLO stop voltage
R
4.5V
) after the SenseFET turns on.
Protection Block
V
ref
400µA
OLP
R
+
-
TSD
OSC
OSC
OLP
A /R
CC
S
R
capacitor via the
S
R
driver
Gate
Q
Q
Protection Block
www.fairchildsemi.com
OLP, TSD
DRIVER
GATE
SENSE
FB
is