CY7C1512V18-167BZC Cypress Semiconductor Corp, CY7C1512V18-167BZC Datasheet - Page 23

• Manufacturer Part Number: CY7C1512V18-167BZC
• Description: IC SRAM 72MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512V18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Notes
Document #: 38-05489 Rev. *F
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
22. This part has a voltage regulator internally; t
23. For D0 data signal on CY7C1525V18 device, t
24. t
25. At any voltage and temperature t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
operated and outputs data with the output timings of that frequency range.
state voltage.
[23]
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
V
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Setup to (K/K) Clock Rise
Control Setup to K Clock Rise (RPS, WPS)
DDR Control Setup to Clock (K/K) Rise
(BWS
D
Address Hold after (K/K) Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
DDR Control Hold after Clock (K/K) Rise
(BWS
D
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C/C) Rise to High-Z (Active to High-Z)
Clock (C/C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
DD
[X:0]
[X:0]
[20, 21]
CHZ
(Typical) to the First Access
Hold after Clock (K/K) Rise
0
Setup to Clock (K/K) Rise
0
, BWS
, BWS
is less than t
POWER
1
1
SD
, BWS
, BWS
is 0.5 ns for 200 MHz, and 250 MHz frequencies.
CLZ
is the time that the power must be supplied above V
and t
2
2
, BWS
, BWS
CHZ
Description
[24, 25]
less than t
3
3
)
)
[22]
AC Test Loads and Waveforms
CO
.
[24, 25]
CY7C1510V18, CY7C1525V18
CY7C1512V18, CY7C1514V18
DD
on page 22. Transition is measured ± 100 mV from steady
minimum initially before initiating a read or write operation.
–0.45
–0.45
–0.30
–0.45
1024
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
Min Max Min Max Min Max
4.0
1.6
1.6
1.8
250 MHz
30
1
0
–
–
–
–
–
0.45
0.45
0.30
0.45
0.20
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.35
–0.45
1024
5.0
2.0
2.0
2.2
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
200 MHz
30
1
0
–
–
–
–
–
0.45
0.45
0.35
0.45
0.20
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.50
–0.50
–0.40
–0.50
1024
6.0
2.4
2.4
2.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
167 MHz
30
0
–
1
–
–
–
–
Page 23 of 29
0.50
0.50
0.40
0.50
0.20
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Cycles
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback