CY7C09569V-83AXC Cypress Semiconductor Corp, CY7C09569V-83AXC Datasheet - Page 2

• Manufacturer Part Number: CY7C09569V-83AXC
• Description: IC SRAM 576KBIT 83MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-83AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 83MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06054 Rev. *B
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3V
synchronous CMOS 16K and 32K x 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid t
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
external R/W LOW duration. The internal write pulse is self-
timed to allow the shortest possible cycle times.
CD1
= 12.5 ns after
CD2
= 5 ns
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the
pipelined mode, one cycle is required with CE LOW to
reactivate the outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 144-Pin Thin Quad Plastic Flatpack
(TQFP), 144-Pin Pb-Free Thin Quad Plastic Flatpack (TQFP)
and 172-Ball Ball Grid Array (BGA) packages.
CY7C09569V
CY7C09579V
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