MT45W8MW16BGX-701 WT TR Micron Technology Inc, MT45W8MW16BGX-701 WT TR Datasheet
MT45W8MW16BGX-701 WT TR
Specifications of MT45W8MW16BGX-701 WT TR
Related parts for MT45W8MW16BGX-701 WT TR
MT45W8MW16BGX-701 WT TR Summary of contents
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... Operating temperature range – Wireless (–30°C to +85°C) – Industrial (–40°C to +85°C) GX Notes: 1. The 3.6V I/O and the 133MHz clock fre- –70 –85 MT45W8MW16BGX-7013LWT Micron Technology, Inc., reserves the right to change products or specifications without notice 1.5 54-Ball VFBGA Ball Assignment 1 ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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... General Description Micron developed for low-power, portable applications. The MT45W8MW16BGX device has a 128Mb DRAM core, organized as 8 Meg x 16 bits. These devices include an industry- standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM offerings. ...
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... Functional block diagrams illustrate simplified device operation. See ball descriptions (Table 1 on page 7), bus operations table (Table 2 on page 8), and timing diagrams for detailed information. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Address Decode 8,192K x 16 Logic DRAM Memory ...
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... Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Input Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Input Lower byte enable. DQ[7:0] Input Upper byte enable ...
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... CLK ADV# CE# OE 0V; all device balls must be static (unswitched) in order to achieve standby cur Page/Burst CellularRAM 1.5 Memory LB#/ 2 WE# CRE UB# WAIT DQ[15: Low-Z Data-out Low-Z Data- High Low Low Low-Z Config. reg. out High-Z LB#/ 2 WE# CRE UB# WAIT DQ[15: Low-Z Data-out Low-Z Data-in ...
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... CSN-11, “Product Mark/Label,” at http://www.micron.com/csn. 3. The 3.6V I/O exceeds the CellularRAM 1.5 Workgroup specification of 1.95V. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory -70 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Functional Description In general, the MT45W8MW16BGX device is a high-density alternative to SRAM and pseudo-SRAM products, popular in low-power, portable applications. The MT45W8MW16BGX contains a 134,217,728-bit DRAM core, organized as 8,388,608 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. ...
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... OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Address Valid Data Valid READ cycle time < t CEM Address Valid Data Valid WRITE cycle time Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory < t CEM Add 0 Add 1 Add 2 Add APA t APA D0 D1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated and de-asserts to indicate when data transferred into (or out of ) the memory. WAIT will again be asserted at the boundary of the 128-word row unless wrapping within the burst length. ...
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... Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Address Valid Latency Code 2 (3 clocks) READ Burst Identified ...
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... LOW during the entire WRITE operation. CE# can remain LOW when transi- tioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed to legacy burst mode Flash memory controllers. See Figure 50 on page 62 for the “Asyn- chronous WRITE Followed by Burst READ” timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system- level WAIT signal ...
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... Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice ...
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... Registers Two user-accessible configuration registers define the device operation. The BCR defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The RCR is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state ...
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... HIGH. (See Figures 12 through 15 on pages 18 through 21.) When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[22:0 asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Latch Control Register Address Page/Burst CellularRAM 1.5 Memory Address Address t CBPH 3 High-Z Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... AVH t AVS AAVD Initiate Register Access OLZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 Page/Burst CellularRAM 1.5 Memory Address Address t CPH OHZ t BHZ CR Valid Data Valid Don’t Care ©2004 Micron Technology, Inc. All rights reserved. Undefined ...
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... Latch Control Register Address ABA t BOE OLZ t ACLK CR Valid t KOH 21 Page/Burst CellularRAM 1.5 Memory Address Address t CBPH OHZ High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Data Valid ...
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... OE# WE# LB#/UB# DATA Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or 0001h. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory ...
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... OE# WE# LB#/UB# DATA Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h, 0001h, or 0002h. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory ...
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... Bus Configuration Register (BCR) The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 describes the control bits in the BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b or through the register access software sequence with DQ = 0001h on the third cycle ...
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... Yes ... 14 15 ... 30 31 PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory 8-Word 16-Word Burst Length Burst Length Linear Linear 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12- 13-14-15 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0-1 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14- ...
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... The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment ...
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... The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[ data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively ...
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... Latency Refresh Normal Collision — — 28 Page/Burst CellularRAM 1.5 Memory BCR[ Data valid in current cycle. BCR[ Data valid in next cycle. Don’t Care Max Input CLK Frequency (MHz) -7013 -701 -708 66 (15.0ns) 66 (15ns) 52 (19.2ns) 104 (9.62ns) 104 (9.62ns) 80 (12.5ns) 133 (7.5ns) — ...
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... Valid Output Code 3 (Default (19.2ns (13.3ns) 6 104 (9.62ns) 8 133 (7.5ns) — 29 Page/Burst CellularRAM 1.5 Memory Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Don’t Care Max Input CLK Frequency (MHz) -7013 -701 -708 33 (30ns) 33 (30ns) 33 (30ns) 52 (19 ...
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... Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asyn- chronous mode of operation. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory N-1 Cycles Cycle AADV ...
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... DQ = 0000h on the third cycle. (See “Registers” on page 17.) PAR (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system ...
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... Notes: 1. Vendors with 256-word row lengths for CellularRAM 1.5 devices will set DIDR[15] to 1b. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Active Section Address Space Full die 000000h–7FFFFFh One-half of die 000000h– ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ –0.5V to (4. relative voltage exceeds the 2.45V CellularRAM 1.5 Workgroup CC 33 Page/Burst CellularRAM 1.5 Memory Rating Q + 0.3V, whichever is less) CC –0.2V to +2.45V 1 –0.2V to +4.0V –55ºC to +150ºC –30ºC to +85ºC –40ºC to +85ºC +260º ...
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... Q + 1.0V for periods less than 2ns during transitions 1.0V for periods less than 2ns during transitions. SS (MAX) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve (TYP) is the average I at 25°C and Page/Burst CellularRAM 1.5 Memory < +85ºC) C Min Max Unit 1.7 1.95 1.7 3 ...
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... CC Low-power option (L) (MAX) values measured at 85°C. In order to achieve low standby current, all inputs PAR ) TCR Temperature (°C) 35 Page/Burst CellularRAM 1.5 Memory Array Partition Max Full 200 1/2 170 1/4 155 1/8 150 0 140 Full 160 1/2 130 1/4 115 ...
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... Q/2 Test Points for a logic 1 and V CC Q/2. CC Q/2. CC Test Point 50Ω VccQ/2 30pF 36 Page/Burst CellularRAM 1.5 Memory Typ Max Min Max 2 3 Q/2 Output CC Q for a logic 0. Input rise and fall SS Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Symbol AADV t APA t AVH t AVS BHZ t BLZ t CEM t CEW CVS OHZ t OLZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 37 Page/Burst CellularRAM 1.5 Memory 70ns 85ns Min Max Min Max 7 ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 36. The Low-Z timings measure a 100mV transition away from the High-Z (V either V PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory -7013 -701 (133 MHz) (104 MHz) Symbol ...
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... Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Symbol AVH t AVS CEW t CPH t CVS WHZ WPH CEM (4µs). Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 Page/Burst CellularRAM 1.5 Memory 70ns 85ns Min Max Min Max 7 ...
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... Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 36. The High-Z timings measure a 100mV transition from either V PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory -7013 (133 MHz) (104 MHz) Symbol ...
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... PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async 1. DPD t DPDX DPD exit Symbol t DPD t DPDX Page/Burst CellularRAM 1.5 Memory V (MIN) CC Device ready for normal operation t PU Device initialization Device ready for normal operation -701/708 -856 Min Max Min ...
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... Figure 30: Asynchronous READ A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Valid Address OLZ V t BLZ High CEW V OH High Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 31: Asynchronous READ Using ADV# A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory V IH Valid Address AVS t AVH AADV CVS OLZ t BLZ High CEW V OH High-Z ...
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... Figure 32: Page Mode READ A[22:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Valid Address Valid Valid Address Address CEM OLZ BLZ t APA Valid High-Z Output ...
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... A[22:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory CLK KHKL ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ t KHKL t CLK t CEM t ABA t BOE t OLZ t KHTL t ACLK Valid High-Z Output 46 Page/Burst CellularRAM 1.5 Memory KOH Valid Valid Valid Output Output Output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async CLK t AVH AADV t CEM High-Z Micron Technology, Inc., reserves the right to change products or specifications without notice. 47 Page/Burst CellularRAM 1.5 Memory KHKL BOE OHZ t OLZ KHTL t t ACLK KOH Valid Output Don’ ...
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... KHKL t CLK AADV t CEM BOE t OLZ t KHTL t ACLK Valid High-Z Output 48 Page/Burst CellularRAM 1.5 Memory KOH Valid Valid Valid Output Output Output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... OHZ t BOE t KOH Valid Valid Valid Valid Output Output Output Output 49 Page/Burst CellularRAM 1.5 Memory Note 2 Note BOE t OLZ Valid Valid Output Output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE HIGH one cycle sooner than shown here. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Note KHTL Valid ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address CE WPH High WHZ CEW V OH High Page/Burst CellularRAM 1.5 Memory CPH Valid Input t HZ High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address WPH High WHZ CEW V OH High Page/Burst CellularRAM 1.5 Memory Valid Input t HZ High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address WPH High WHZ CEW V OH High Page/Burst CellularRAM 1.5 Memory Valid Input High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address AVS t AVH CVS High WHZ CEW V OH High Page/Burst CellularRAM 1.5 Memory t WPH Valid Input High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... WAIT active LOW; WAIT asserted during delay; burst length of four; burst-wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency latency code (BCR[13:11]). required if PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory t CLK CEM t KHTL Note CSP > ...
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... WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency latency code (BCR[13:11]). required if PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory t CLK AVH CEM t KHTL Note ...
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... Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE HIGH one cycle sooner than shown here. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Note KHTL Note 3 Valid Input ...
Page 58
... CEM. See burst interrupt diagrams (Figures 47 through 49, on Micron Technology, Inc., reserves the right to change products or specifications without notice. 58 Page/Burst CellularRAM 1.5 Memory BOE t KOH t ACLK Valid Valid Valid High-Z Output Output Output Don’t Care t CEM. A refresh opportunity is satisfied by ©2004 Micron Technology, Inc. All rights reserved. ...
Page 59
... Cycle WRITE V IL LB#/UB 2nd Cycle WRITE V IL DQ[15: High-Z 2nd Cycle WRITE V IL Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 Page/Burst CellularRAM 1.5 Memory t BOE t KOH Valid Valid Valid Valid Output Output Output Output t ACLK Don’ ...
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... CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t CEM. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory WRITE Burst interrupted with new WRITE or READ. See Note 2. t CLK Valid Address ...
Page 61
... CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t CEM. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory WRITE Burst interrupted with new WRITE or READ. See Note 2. t CLK t SP Valid Address ...
Page 62
... Note CEW t ACLK V OH Data High CEM. A refresh opportunity is satisfied by either of the 62 Page/Burst CellularRAM 1.5 Memory BOE t KOH Valid Valid Valid Valid Output Output Output Output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
Page 63
... CBPH t CSP Note CEW VOH Data High-Z VOL t CEM. A refresh opportunity is satisfied by either of the 63 Page/Burst CellularRAM 1.5 Memory t BOE t KOH t ACLK Valid Valid Valid Output Output Output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 64
... HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs; asynchro- nous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every clocked CE# HIGH CE# HIGH for longer than 15ns. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory t CLK CBPH ...
Page 65
... ADV#. A refresh opportunity must be provided every clocked CE# HIGH CE# HIGH for longer than 15ns. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory t CLK CBPH t HZ Note 2 t OHZ ...
Page 66
... Valid Address CPH Note High-Z Data CPH) to schedule the appropriate refresh interval. Otherwise, Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 Page/Burst CellularRAM 1.5 Memory Valid Address BLZ OLZ V OH Valid Output V OL Don’t Care t CPH is only required © ...
Page 67
... WP t WPH V OH Data Data CPH) to schedule the appropriate refresh interval. Otherwise, 67 Page/Burst CellularRAM 1.5 Memory Valid Address BLZ OLZ t OE Valid Output High-Z Don’t Care Undefined t CPH is only required Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W8MW16BGX uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...