AT24C64AN-10SI-2.7 Atmel, AT24C64AN-10SI-2.7 Datasheet - Page 9

• Manufacturer Part Number: AT24C64AN-10SI-2.7
• Description: IC EEPROM 64KBIT 400KHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT24C64AN-10SI-2.7

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT24C64AN-10SI2.7

Device Addressing
Write Operations
3054T–SEEPR–1/07
The 32K/64K EEPROM requires an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see Figure 7 on page 11). The device
address word consists of a mandatory one, zero sequence for the first four most signifi-
cant bits as shown. This is common to all 2-wire EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them
to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins pre-
vent small noise spikes from activating the device.
DATA SECURITY: The AT24C32A/64A has a hardware data protection scheme that
allows the user to write protect the entire memory when the WP pin is at V
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle, t
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 11).
PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 31
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 11).
The data word address lower five bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 32 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
CC
.
WR
, to the
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