AT27C2048-12VI Atmel, AT27C2048-12VI Datasheet - Page 2

• Manufacturer Part Number: AT27C2048-12VI
• Description: IC OTP 2MBIT 120NS 40VSOP
• Manufacturer: Atmel

Specifications of AT27C2048-12VI

• Format - Memory: EPROMs
• Memory Type: OTP EPROM
• Memory Size: 2M (128K x 16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT27C204812VI

In read mode, the AT27C2048 typically consumes 15 mA.
Standby mode supply current is typically less than 10 A
The AT27C2 048 is av ai lab le in ind us try s tand ar d
JEDEC-approved one-time programmable (OTP) plastic
PDIP, PLCC, and VSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in
high-speed systems.
With high density 128K word storage capability, the
AT27C2048 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure
high quality and efficient production use. The Rapid
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50 s/word. The Integrated Prod-
uct Identification Code electronically identifies the device
and manufacturer. This feature is used by industry stan-
Block Diagram
2
AT27C2048
ADDRESS
A0 - A17
INPUTS
VCC
GND
VPP
OE
CE
PROGRAM LOGIC
Y DECODER
X DECODER
OE, CE AND
™
Pro-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the V
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7 µF bulk electrolytic capacitor should
be utilized, again connected between the V
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
IDENTIFICATION
CC
DATA OUTPUTS
CELL MATRIX
and Ground terminals of the device, as
BUFFERS
Y-GATING
OUTPUT
O0 - O15
CC
and Ground