IDT70T3539MS166BC IDT, Integrated Device Technology Inc, IDT70T3539MS166BC Datasheet - Page 10

• Manufacturer Part Number: IDT70T3539MS166BC
• Description: IC SRAM 18MBIT 166MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70T3539MS166BC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70T3539MS166BC

AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
NOTES:
1. The Pipelined output parameters (t
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
3. These values are valid for either level of V
4. Guaranteed by design (not production tested).
Port-to-Port Delay
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
INS
INR
COLS
COLR
ZZSC
ZZRC
CO
OFS
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
apply when FT/PIPE = V
treated as DC signals, i.e. steady state during operation.
Symbol
(6)
(6)
(6)
(6)
Clock Cycle Time (Flow-Through)
Clock Cycle Time (Pipelined)
Clock High Time (Flow-Through)
Clock Low Time (Flow-Through)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)
Clock to Data Valid (Pipelined)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
Clock-to-Clock Offset
Clock-to-Clock Offset for Collision Detection
Address Setup Time
Address Hold Time
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
REPEAT Setup Time
REPEAT Hold Time
ss
(0V) for that port.
CYC2
, t
(1)
(2)
CD2
(1)
(1)
DDQ
(1)
) apply to either or both left and right ports when FT/PIPE
(1)
(1)
(1)
(3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
Parameter
(2,3)
(V
6.42
10
DD
= 2.5V ± 100mV, T
Industrial and Commercial Temperature Ranges
Please refer to Collision Detection Timing Table on Page 19
X
Min.
= V
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
____
____
____
____
____
____
____
70T3539MS166
20
6
8
8
2
3
5
1
1
1
1
1
Com'l Only
DD
(2.5V). Flow-through parameters (t
Max.
A
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
4.4
____
3.6
3.6
____
3.6
____
3.6
3.6
____
____
____
12
7
7
= 0°C to +70°C)
Min.
7.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
____
____
____
____
____
____
____
25
70T3539MS133
10
10
3
3
2
3
6
1
1
1
1
1
Com'l
& Ind
Max.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
4.6
____
4.2
4.2
____
4.2
____
4.2
4.2
____
____
____
15
7
7
CYC1
, t
CD1
cycles
cycles
5678 tbl 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)